sab-c161ji-lf Infineon Technologies Corporation, sab-c161ji-lf Datasheet
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Edition 2001-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms ...
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C161CS/JC/JI Revision History: Previous Version: Page Subjects (major changes since last revision) All Converted to Infineon layout 2 Derivative Synopsis Table updated 4, 6, 10, 18 Programmable Interface Routing introduced 27, 28 GPT block diagrams updated 29 RTC description improved ...
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Single-Chip Microcontroller C166 Family C161CS/JC/JI • High Performance 16-bit CPU with 4-Stage Pipeline – Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to ...
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... Derivative SAK-C161CS-32RF SAB-C161CS-32RF SAK-C161CS-LF SAB-C161CS-LF SAK-C161JC-32RF SAB-C161JC-32RF SAK-C161JC-LF SAB-C161JC-LF SAK-C161JI-32RF SAB-C161JI-32RF SAK-C161JI-LF SAB-C161JI-LF For simplicity all versions are referred to by the term C161CS/JC/JI throughout this document. Data Sheet On-Chip Serial Bus Program Memory Interface(s) 256 KByte ROM CAN1, CAN2 --- CAN1, CAN2 ...
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Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the ...
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Pin Configuration (top view) RSTOUT 1 NMI P6.0/CS0 5 P6.1/CS1 6 P6.2/CS2 7 P6.3/CS3 8 P6.4/CS4 9 P6.5/HOLD 10 P6.6/HLDA 11 P6.7/BREQ 12 P7.4/CC28IO/* 13 P7.5/CC29IO/* 14 P7.6/CC30IO/* 15 P7.7/CC31IO ...
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Table 2 Pin Definitions and Functions Symbol Pin Input No. Outp. RST 1 O OUT NMI P6.6 11 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P7 P7 P7 P7 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P5.12 37 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P2.8 43 I/O I P2.9 44 I/O I P2.10 45 I/O I P2.11 46 I/O I P2.12 47 I/O I P2.13 48 I/O I P2.14 49 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P3 P3 I ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp. READY 82 I ALE PORT0 IO P0L.0-7 85- 92 P0H.0-7 95- 102 Data Sheet Function Ready Input. When the Ready function is enabled, ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp. PORT1 IO P1L.0-7 103- 110 P1H.0-7 113- 120 P1H.4 117 I/O P1H.5 118 I/O P1H.6 119 I/O P1H.7 120 I/O XTAL2 123 O XTAL1 124 I XTAL3 126 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp. RSTIN 128 I – AREF V 36 – AGND V 4, 18, – 42, 52, 68, 78, 93, 111, 121 V 3, ...
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Note: The following behavioural differences must be observed when the bidirectional reset is active: • Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. • The reset indication flags always indicate a ...
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... X-Peripherals (see The XBUS resources (XRAM, CAN, SDLM, IIC, ASC1) of the C161CS/JC/JI can be enabled during initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). If the X-Peripherals remain disabled they consume neither address space nor port pins. Data Sheet C166-Core 32 ...
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... KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. ...
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...
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... Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines can be used to increase the total amount of addressable external memory. Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs ...
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The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...
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Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C161CS/JC/JI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...
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Table 3 C161CS/JC/JI Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...
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Table 3 C161CS/JC/JI Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...
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The C161CS/JC/JI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse ...
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When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode CPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 8 Capture ...
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of ...
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This allows the C161CS/JC/JI to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN ...
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Real Time Clock The Real Time Clock (RTC) module of the C161CS/JC/JI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). ...
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... In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via register P5DIDIS (Port 5 Digital Input Disable). Data Sheet C161CS/JC/JI-32R ...
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... The ASC1 is function compatible with the ASC0, except that its registers are not bit- addressable (XBUS peripheral) and it provides only three interrupt vectors. The SSC supports full-duplex synchronous communication 6.25 MBaud (@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components ...
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... Note: When the SDLM is used with the interface lines assigned to Port 4, the interface lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines can be used to increase the total amount of addressable external memory. Data Sheet C161CS/JC/JI-32R ...
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... Note: When one or both of the on-chip CAN Modules are used with the interface lines assigned to Port 4, the interface lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines can be used to increase the total amount of addressable external memory. IIC Module The integrated IIC Bus Module handles the transmission and reception of frames over the two-line IIC bus in accordance with the IIC Bus specification ...
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... Parallel Ports The C161CS/JC/JI provides I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...
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... The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows ...
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... Slow Down Mode lets the C161CS/JC/JI run at a CPU clock frequency of 1 … 32 (half for prescaler operation) which drastically reduces the consumed power. The PLL can be optionally disabled while operating in Slow Down Mode. External circuitry can be controlled via the programmable frequency output FOUT. ...
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... BAND, BOR, AND/OR/XOR direct bit with direct bit BXOR BCMP Compare direct bit to direct bit BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 ...
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... Software Reset IDLE Enter Idle Mode PWRDN Enter Power Down Mode (supposes NMI-pin being low) SRVWDT Service Watchdog Timer DISWDT Disable Watchdog Timer EINIT Signify End-of-Initialization on RSTOUT-pin ATOMIC Begin ATOMIC sequence EXTR Begin EXTended Register sequence EXTP(R) Begin EXTended Page (and Register) sequence ...
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... Table 7 lists all SFRs which are implemented in the C161CS/JC/JI in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “ ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address C1PCIR EF02 H C1LARn EFn4 H C1LGML EF0A H C1LMLM EF0E H C1MCFGn EFn6 H C1MCRn EFn0 H C1UARn EFn2 H C1UGML EF08 H C1UMLM EF0C H C2BTR EE04 ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address CC13IC b FF92 H CC14 FE9C H CC14IC b FF94 H CC15 FE9E H CC15IC b FF96 H CC16 FE60 H CC16IC b F160 H CC17 FE62 H CC17IC ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address CC28IC b F178 H CC29 FE7A H CC29IC b F184 H CC2IC b FF7C H CC3 FE86 H CC30 FE7C H CC30IC b F18C H CC31 FE7E H CC31IC ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address CRIC b FF6A H CSP FE08 H DP0H b F102 H DP0L b F100 H DP1H b F106 H DP1L b F104 H DP2 b FFC2 H DP3 b ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address IDPROG F078 H IFR EB18 H INTCON EB2C H IPCR EB04 H ISNC F1DE H MDC b FF0E H MDH FE0C H MDL FE0E H ODP2 b F1C2 H ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address PECC7 FECE H PICON b F1C4 H POCON0H F082 H POCON0L F080 H POCON1H F086 H POCON1L F084 H POCON2 F088 H POCON20 F0AA H POCON3 F08A H POCON4 ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address RXD18 EB58 H S0BG FEB4 H S0CON b FFB0 H S0EIC b FF70 H S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C H S0TBUF FEB0 H S0TIC ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address SYSCON b FF12 H SYSCON1 b F1DC H SYSCON2 b F1D0 H SYSCON3 b F1D4 H T0 FE50 H T01CON b FF50 H T0IC b FF9C H T0REL FE54 ...
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Table 7 C161CS/JC/JI Registers, Ordered by Name (cont’d) Name Physical Address T8 F052 H T8IC b F17C H T8REL F056 H TFR b FFAC H TRANSSTAT EB1E H TXCNT EB3C H TXCPU EB3E H TXD0 EB30 H TXD10 EB3A H ...
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Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD respect to ground ( Voltage on any pin with V respect to ground ( ) SS Input ...
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... V or < > 0 C161CS/JC/JI-32R C161CS/JC/JI-L Unit Notes V Active mode MHz CPUmax V PowerDown mode V Reference voltage 2)3)4) mA Per pin Pin drivers in fast edge mode C SAB-C161CS/JC/JI … C SAF-C161CS/JC/JI … C SAK-C161CS/JC/JI … - 0.5 V). The absolute sum of input overload V3.0, 2001-01 5) ...
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161CS/ JC/JI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in ...
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DC Characteristics (cont’d) (Operating Conditions apply) Parameter Output low voltage (all other outputs) 5) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 5) Output high voltage (all other outputs) Input leakage current (Port 5) Input ...
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... PLL off, SDD factor = 32 Sleep and Power-down mode supply current with RTC running on main oscillator Sleep and Power-down mode supply current with RTC disabled 1) The supply current is a function of the operating frequency. This dependency is illustrated in These parameters are tested ...
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I µA 1500 1250 1000 750 500 250 I IDOAmax 0 0 Figure 9 Idle and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet I IDOMmax I IDOMtyp I PDRMmax I PDOmax C161CS/JC/JI-32R ...
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I [mA] 100 Figure 10 Supply/Idle Current as a Function of Operating Frequency Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L I DD5max I DD5typ I IDX5max I IDX5typ 25 f [MHz] CPU V3.0, 2001-01 ...
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AC Characteristics Definition of Internal Timing The internal operation of the C161CS/JC/JI is controlled by the internal CPU clock Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the ...
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P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 10 associates the combinations of these three bits with the respective clock generation mode. Table 10 C161CS/JC/JI Clock Generation Modes CLKCFG CPU ...
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The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As ...
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... Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock ...
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AC Characteristics External Clock Drive XTAL1 (Main Oscillator) (Operating Conditions apply) Table 11 External Clock Drive Characteristics Parameter Symbol t Oscillator period OSCM 2) High time Low time 2 2) Rise time ...
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AC Characteristics External Clock Drive XTAL3 (Auxiliary Oscillator) (Operating Conditions apply) Table 12 AC Characteristics Parameter Symbol t Oscillator period OSCA High time Low time 2 Rise time Fall time 4 1) The clock ...
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A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source ...
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During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach its final voltage level within After the end of the sample time result. Values for the sample time t S ...
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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at Figure 14 Input Output Waveforms V + 0.1 V ...
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Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 15 ...
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Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter RD, WR low time (no RW-delay valid data in (with RW-delay valid data in (no RW-delay) ALE low to valid data ...
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Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) ...
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ALE CSxL A23-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A23-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet ...
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ALE CSxL A23-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 18 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A23-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 19 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet ...
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AC Characteristics Demultiplexed Bus (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, ...
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Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE falling edge to CS ...
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Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data float after RdCS 1) (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS 1) RW-delay and t refer to the next following ...
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ALE CSxL A23-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 20 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A23-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 21 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet ...
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ALE CSxL A23-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A23-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 23 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet ...
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AC Characteristics CLKOUT and READY (Operating Conditions apply) Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold ...
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CLKOUT ALE Command RD, WR Sync READY t 58 Async 3) READY Figure 24 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on ...
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AC Characteristics External Bus Arbitration (Operating Conditions apply) Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals ...
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CLKOUT t 61 HOLD HLDA see BREQ CSx (On P6.x) Other Signals Figure 25 External Bus Arbitration, Releasing the Bus Notes 1) The C161CS/JC/JI will complete the currently running bus cycle before granting bus access. 2) This is the first ...
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CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Figure 26 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...
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Package Outline P-TQFP-128-2 (Plastic Thin Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet C161CS/JC/JI-32R 84 C161CS/JC/JI-L Dimensions in mm V3.0, ...
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