sab-c161ji-lf Infineon Technologies Corporation, sab-c161ji-lf Datasheet - Page 39

• Manufacturer Part Number: sab-c161ji-lf
• Description: 16-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 20 s and 671 ms can be
monitored (@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (
In prescaler mode the PLL base frequency is divided by 2 (
Note: The CPU clock source is only switched back to the oscillator clock after a
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of an external reset (EA = ‘0’) bit OWDDIS reflects the inverted level of
Data Sheet
hardware reset.
pin RD at that time. Thus the oscillator watchdog may also be disabled via
hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration via PORT0. At the end of an internal reset (EA = ‘1’)
bit OWDDIS is cleared.
35
f
CPU
f
CPU
= 1 … 2.5 MHz).
C161CS/JC/JI-32R
= 2 … 5 MHz).
C161CS/JC/JI-L
V3.0, 2001-01