st802rt1a STMicroelectronics, st802rt1a Datasheet
st802rt1a
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st802rt1a Summary of contents
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... With auto MDIX, the ST802RT1x automatically detects what is on the other end of the network cable and switches the TX & RX pin functionality accordingly. Temperature range - 40 to 105 ° 105 °C Doc ID 17049 Rev 1 ST802RT1A ST802RT1B LQFP48 Package LQFP48 LQFP48 1/58 www.st.com ...
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... Loop-back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6 Full-duplex and half-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.7 Auto-negotiation operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.8 Power-down / interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9 Power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.10 Interrupt mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.11 LED display operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.12 Reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.13 Preamble suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.14 Remote fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.15 Transmit isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B 7.16 Automatic MDI / MDIX feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.17 RMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.18 FX mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.19 FX operation detect circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.20 PECL transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.21 PECL receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.22 Far-end-fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.23 MII management interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8 Electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Doc ID 17049 Rev 1 Contents 3/58 ...
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... Table 30. RS1B [0d27, 0x1B]: Misc status/error/test shadow register . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 31. LED configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 32. Configuration of signal detect voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 33. Management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 34. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 35. General DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 36. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 37. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B List of figures Figure 1. ST802RT1x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. System diagram of the ST802RT1A Figure 3. System diagram of the ST802RT1B in FX mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Pin configuration - ST802RT1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Pin configuration - ST802RT1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. LED connections Figure 7. Transmit isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 8. PECL levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 9. Implementation of the PECL TX section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 10 ...
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... Auxiliary mode 2 register (RN1B[9]). Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the pin is pulled up or down. See Table 26 and paragraph 1.3 Package ● 48-pin LQFP ( mm.). 6/58 7.11 for more details of LED mode selection. Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B 2 Device block diagram Figure 1. ST802RT1x block diagram 10BASE-T 10BASE-T 100BASE-TX 100BASE-TX 100BASE-FX 100BASE-FX TX CHANNEL TX CHANNEL TRANSMITTER TRANSMITTER HW HW CONFIG CONFIG HW PROG PINS HW PROG PINS Serial management Serial management MII/RMII INTERFACES MII/RMII INTERFACES INTERFACE INTERFACE CONTROLLER CONTROLLER REGISTERS REGISTERS AUTO ...
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... System and block diagrams 3 System and block diagrams Figure 2. System diagram of the ST802RT1A/B Figure 3. System diagram of the ST802RT1B in FX mode 8/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B 4 Pin configuration Figure 4. Pin configuration - ST802RT1A TX_CLK/LPBK_EN TX_CLK/LPBK_EN TX_EN TX_EN GNDA GNDA VCCA VCCA TXD0 TXD0 TXD1 TXD1 ...
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... Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B DVDD DVDD DVDD DVDD 36 36 ...
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... Ground Analog ground I/O Reference resistor/ DC regulator output (bias resistor) Supply Analog power supply Ground Analog ground Supply Analog power supply - Not used in the ST802RT1A Positive signal detect for 100Base-FX operation (ST802RT1B I only Activity/full-duplex/collision led Speed LED Link LED I ...
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... Receive data (MII)/Phy3 Receive data (MII/RMII)/Phy2 Receive data (MII/RMII)/Phy1 MII collision detection/Phy0 Ground Ground - Not used in the ST802RT1A I Negative signal detect (100Base-FX only) Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B Description Description Input Output Input/output Strap option ...
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... ST802RT1A, ST802RT1B Table 4. Pin functions of the ST802RT1x Pin n° Name Type Data interface 5 TXD0 6 TXD1 I 7 TXD2 8 TXD3 7 SCLK I 2 TX_EN TX_CLK RXER O 42 RXD3 43 RXD2 RXD1 45 RXD0 RXDV / CRSDV 37 RX_CLK O 46 COL O 39 CRS O MII control interface ...
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... The PECL logical low level (PECL the PECL logical middle level (PECL PECL logical high level (PECL HIGH RESERVED in ST802RT1A the pins must be grounded through a 1.2 kΩ resistor Differential receive inputs (100Base-TX, 10Base-T). These pins directly output to the transformer. When MDIX is enabled they can work as TXP/TXN Reference resistor/DC regulator output. Reference resistor connecting pin for reference current, directly connect a 5.25 kΩ ...
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... ST802RT1A, ST802RT1B Table 4. Pin functions of the ST802RT1x (continued) Pin n° Name Type 3, 16, 19, 20, GNDA Ground Analog ground 23 Strap pins The ST802RT1x uses many of the functional pins as strap options. The values of these pins are sampled during reset hardware or power-up and used to strap the device into specific modes of operation. ...
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... LOW PECL HIGH PECL FX mode asserted, link OK, and data valid HIGH mii_cfg0 an_en an_en Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B Mode TX mode Undefined state Undefined state Undefined state mii_cfg1 an_0 an_1 an_0 ...
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... ST802RT1A, ST802RT1B 6 Registers and descriptors description All of the management data control and status registers in the ST802RT1x's register set are accessed via a Write or Read operation on the serial MDIO port. This access requires a protocol described in the MII management interface section. 6.1 Register list Table 8. ...
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... Normal operation 1 -> full-duplex operation 8 Duplex mode 0 -> Half-duplex operation Ignored if auto-negotiation is enabled 18/58 Description Read/write Read only Self-clearing Constant Bit with strap value Latched high Latched low Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type type Strap RW - Strap RW - Strap RW - ...
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... ST802RT1A, ST802RT1B Table 10. RN00 [0d00, 0x00]: Control register (continued) Bit Bit name 1 -> Collision test enabled 7 Collision test 0 -> Normal operation Active only in loop-back mode (RN00[14]=1) 6 RESERVED Not used 5 RESERVED Not used 4 RESERVED Not used 3 RESERVED Not used 2 RESERVED Not used ...
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... When this bit is read, it returns a “1” when the collision test mode has been enabled; otherwise it returns a “0”. This bit should only be set while in loop-back test mode. Reserved bits: Write ignored, read as 0. 20/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B Table 11. RN01 [0d01, 0x01]: Status register Bit Bit name 100BASE-T4 0 -> PHY not able to perform 100BASE-T4 15 ABILITY Fixed to 0 100BASE-X 1 -> PHY able to perform full-duplex 100BASE-X 14 Full Duplex Fixed to 1, internally not used 100BASE-X 1 -> PHY able to perform half-duplex 100BASE-X ...
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... OUI LSBs Organizationally unique identifier (OUI), bits 19..24 MODEL 9:4 Manufacturer’s model number NUMBER REVISION Allows identification of the revision of the device via software 3:0 NUMBER reading of the register 22/58 Description Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type type 0203h Default Type type 100001b RO P ...
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... ST802RT1A, ST802RT1B Table 14. RN04 [0d04, 0x04]: Auto-negotiation advertisement register Bit Bit name 1 -> Next page transfer supported 15 Next Page 0 -> Next page transfer not supported 14 RESERVED --- 1 -> Advertises that this device has detected a remote fault 13 Remote Fault during auto-negotiation 0 -> No remote fault detected. ...
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... LP remote fault: Bit 13 of the link partner ability register returns a value of “1” when the link partner signals that a remote fault has occurred. The ST802RT1x simply copies the value to this register and does not act upon it. 24/58 Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type type 0 ...
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... ST802RT1A, ST802RT1B Reserved: Ignore when read. LP pause: Indicates that the link partner pause bit is set. LP selector field: Bits 4:0 of the link partner ability register reflect the value of the Link partner's selector field. These bits are cleared any time auto-negotiation is restarted or the chip is reset. ...
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... Previous transmitted LP LCW toggle was 0 11 Toggle 0 -> Previous transmitted LP LCW toggle was 1 Message / It can be a message code (annex 28C, IEEE 802.3u) or 10:0 Unformatted Code an unformatted code, according to value set in RN08[13] Field 26/58 Description Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type type ...
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... ST802RT1A, ST802RT1B Next page: Indicates whether this is the last next page. Msg page: Differentiates a message page from an unformatted page. Ack2: Indicates that link partner has the ability to comply with the message. Toggle: Used by the arbitration function to ensure synchronization with the link partner during next page exchange ...
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... Interrupt enabled by RN12[1] 1 -> “receive error buffer full” interrupt is pending (64k packet errors) 0 RX_FULL 0 -> less than 64k error packets received Interrupt enabled by RN12[0]. Related counter is cleared after read 28/58 Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type type 00000b ...
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... ST802RT1A, ST802RT1B Table 21. RN12 [0d18, 0x12]: Receiver event interrupts register Bit Bit name 15:9 RESERVED NOT USED INTERRUPT OUTPUT ENABLE: 8 INT_OE_N 1 -> PWRDWN/MDINT is a power-down input 0 -> PWRDWN/MDINT is an interrupt output INTERRUPT ENABLE: 7 INT_EN 1 -> Event interrupts enabled 0 -> Event interrupts disabled “ ...
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... PHY ADDR Physical address for MDIO management 2 RESERVED -- 1 -> Accepts management frames with preamble Preamble suppressed 1 suppression 0 -> Doesn't accept management frames without preamble 0 RESERVED -- 30/58 Description Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type Type 00b 000b ...
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... ST802RT1A, ST802RT1B Table 24. RN18 [0d24, 0x18]: Auxiliary control register Bit Bit name 1 -> Disables jabber detection (10BaseT) 15 Jabber disable 0 -> Normal operation 14 RESERVED -- 13:8 RESERVED -- 7:5 RESERVED -- MDIO Power 1 -> Stops MDC clock when MDIO interface is idle 4 Saving 0 -> Normal operation 3:0 RESERVED -- Jabber disable: 10BASE-T operation only. Bit 15 of the auxiliary control register allows the user to disable the jabber detect function, defined in the IEEE standard ...
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... Jabber condition detected 0 -> No jabber condition detected. Set at jabber condition detection, cleared only after register 0 Jabber Detect read (if no more jabber condition is present). Fixed 100Base-X modes. Same as RN01[1] 32/58 Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type Type ...
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... ST802RT1A, ST802RT1B Table 26. RN1B [0d27, 0x1B]: Auxiliary mode 2 register Bit Bit name 15:12 RESERVED -- 11:10 RESERVED -- 1 -> led_link pad: ON for link_up, BLINK for activity led_speed pad: ON for 100 Mb, OFF for 10 Mb led_act pad: ON for full-duplex, BLINK for collision 9 LED Mode 0 -> led_link pad: ON for link_up ...
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... MDIX swap: Setting this bit forces the device to MDIX. When this bit is 0, the MDIX status is determined by auto-negotiation if auto-MDIX is enabled. MDIX disable: Setting this bit disables auto-detection and negotiation of MDIX. Clearing this bit enables auto-MDIX. 34/58 Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type Type 00 RW ...
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... ST802RT1A, ST802RT1B Table 28. RN1E [0d30, 0x1E]: Auxiliary PHY register Bit Bit name 1 -> AN 100Base-TX full-duplex selected 15 HCD 100base-Tx FDX 0 -> AN 100Base-TX full-duplex not selected 1 -> AN 100Base-T4 selected (not supported) 0 -> AN 100Base-T4 not selected 14 HCD 100BASE-T4 Internally fixed to '0' HCD 100base-TX 1 -> AN 100Base-TX half-duplex selected ...
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... When this bit is set, registers at addresses 1B are masked Shadow 7 by correspondent shadow registers Registers Enable Self-clearing functionality added to this bit when shadow registers are enabled 6:0 RESERVED Not used 36/58 Description Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B RW Default Type Type 00000000b 0000000b RO ...
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... ST802RT1A, ST802RT1B Table 30. RS1B [0d27, 0x1B]: Misc status/error/test shadow register Bit Bit name 1 -> MLT3 enabled with no errors (TX100 only) 15 MLT3 Detect 0 -> MLT3 disabled or MLT3 error TX100 CABLE LENGTH (m): 000 <= 20 001 = 20-40 010 = 40-60 TX Cable 14:12 011 = 60-80 Length 100 =80-100 101 =100-120 110 = 120-140 111 => ...
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... MLT3 encoder to generate the TP-PMD specified MLT3 code. The MLT3 code lowers the frequency and reduces the energy of the transmission signal in the UTP cable and also allows the system to meet the FCC specification for EMI. 38/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B Wave-shaper and media signal driver: In order to reduce the energy of the harmonic frequency of transmission signals, the device provides the wave-shaper prior to the line driver to smooth out, but maintain symmetric, the rising/falling edge of the transmission signals. The wave-shaped signals include the 100Base-TX and 10Base-T, and both are passed to the same media signal driver ...
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... ST802RT1x and the network partner to automatically configure both to take maximum advantage of their abilities, and both are setup accordingly. The auto-negotiation function can be controlled through auto-negotiation enable bit 12 of the RN00 register, or the an_en strap pin 27. 40/58 th cycle yielding the correct frame data. To Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B Auto-negotiation exchanges information with the network partner using the fast link pulses (FLPs burst of link pulses. FLP’s contain 16 bits of signaling information to advertise all supported capabilities, determined by register RN04 (auto-negotiation advertisement register), to the remote partner. Based on this information, they identify their highest common capability by following the priority sequence below: 1 ...
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... LED speed ON for link-up ON for 100Mb OFF for no link OFF for 10Mb ON for link-up ON for 100Mb OFF for no link OFF for 10Mb Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B contains a detailed description of the ST802RT1x. LED act/col ON for full-duplex BLINK for collision BLINK for activity ...
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... ST802RT1A, ST802RT1B 7.12 Reset operation There are two ways to reset the ST802RT1x. Hardware reset: the ST802RT1x can be reset via the RESET pin (pin 29). The active low reset input signal is required for at least 1 ms, and at least one transition is required on the MDC (pin 31) to ensure proper reset operation. ...
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... MII interface. Since start-of-packet and end-of-packet timing information is preserved across the interface, the MAC is able to derive the COL signal from the receive and transmit data delimiters, saving another pin. 44/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B 7.18 FX mode operation Each port of the ST802RT1x may also be configured for 100BASE-FX transmission over fiber optics via a pseudo-ECL (PECL) interface. In 100Base-Fx mode, scrambling and MLT3-to-binary conversion are bypassed when transmitting, whereas in reception adaptive equalization, binary-to-MLT3 and descrambling are bypassed. ...
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... FX mode asserted, but no data valid on the line LOW PECL FX mode asserted, but no data valid on the line LOW PECL Undefined state HIGH PECL FX mode asserted, link OK and data valid HIGH Figure 8 for the definition of PECL levels. Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B Mode ...
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... ST802RT1A, ST802RT1B Figure 9. Implementation of the PECL TX section 7.21 PECL receiver The data signals coming from the optical transceiver are in PECL format and need to be converted to CMOS level before being transmitted to the data and clock recovery, and to the digital portion. The data is sampled by the optical transceiver, but the data stream is related to the clock of the transmitting transceiver needs to be recovered, re-sampled and aligned to the RX clock ...
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... The data field contains the 16 bits to write to, or read from, the specified register and is followed by at least one IDLE bit which closes the frame. 48/58 Table 33. OP PHYAD REGAD 10 AAAAA RRRRR 01 AAAAA RRRRR Section 7.13. Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B TA DATA IDLE Z0 D… D…D Z ...
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... ST802RT1A, ST802RT1B 8 Electrical specifications and timings Table 34. Absolute maximum ratings Parameter Supply voltage ( Input voltage Output voltage Storage temperature Ambient temperature ESD protection Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. ...
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... Tmih MDIO hold time Tmidco MDIO clock to output delay 50/58 Test conditions 10 Mbps 10 Mbps 10 Mbps MII- 100 Mb/s MII- 100 Mb/s STA sources MDIO STA sources MDIO PHY sources MDIO Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B Min. Typ. Max. Unit 25/50/125 MHz 50 ppm ...
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... ST802RT1A, ST802RT1B Figure 11. Normal link pulse timings Figure 12. Fast link pulse timing Electrical specifications and timings Doc ID 17049 Rev 1 51/58 ...
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... Electrical specifications and timings Figure 13. MII management clock timing 52/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Doc ID 17049 Rev 1 Package mechanical data ® ...
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... Package mechanical data Table 36. LQFP48 mechanical data Dim 54/58 mm Min. Typ. 0.05 1.35 1.4 0.17 0.22 0.09 8.80 9 6.80 7 5.50 8.80 9 6.80 7 5.50 0.50 0.45 0.60 1 0° 3.5° Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B Max. 1.60 0.15 1.45 0.27 0.20 9.20 7.20 9.20 7.20 0.75 7° ...
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... ST802RT1A, ST802RT1B Figure 14. Dimensions of the LQFP48 package Doc ID 17049 Rev 1 Package mechanical data 0110596 55/58 ...
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... Package mechanical data Figure 15. LQFP48 footprint recommended data (mm.) 56/58 Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...
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... ST802RT1A, ST802RT1B 10 Revision history Table 37. Document revision history Date Revision 02-Feb-2010 1 Initial release. Doc ID 17049 Rev 1 Revision history Changes 57/58 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 58/58 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 17049 Rev 1 ST802RT1A, ST802RT1B ...