cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet

cyv15g0404dxb

Manufacturer Part Number

cyv15g0404dxb

Description

Independent Clock Quad Hotlink Ii Transceiver With Reclocker

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CYV15G0404DXB.pdf (44 pages)

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Features

■

Cypress Semiconductor Corporation

Document #: 38-02097 Rev. *B

Quad channel transceiver for 195 to 1500 MBaud serial

signaling rate

❐

Second-generation HOTLink

Compliant to multiple standards

❐

Truly independent channels

❐

Internal phase-locked loops (PLLs) with no external PLL

components

Selectable differential PECL compatible serial inputs per

channel

❐

Redundant differential PECL compatible serial outputs per

channel

❐

MultiFrame™ Receive Framer provides alignment options

❐

Selectable input and output clocking options

Aggregate throughput of up to 12 Gbits/second

SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ES-

CON, and Gigabit Ethernet (IEEE802.3z)

10 bit uncoded data or 8B/10B coded data

Each channel is able to:

• Perform reclocker function

• Operate at a different signaling rate

• Transport a different data format

Internal DC restoration

No external bias resistors required

Signaling rate controlled edge rates

Source matched for 50Ω transmission lines

Comma or full K28.5 detect

Single or multibyte Framer for byte alignment

Low latency option

CYV15G0404DXB

Independent

Reclocker

technology

Channel

Figure 1. HOTLink II™ System Connections

•

198 Champion Court

Independent Clock Quad HOTLink II™

Connections

Serial Links

Cable

■

Functional Description

The CYV15G0404DXB Independent Clock Quad HOTLink II™

Transceiver is a point-to-point or point-to-multipoint communica-

tions building block enabling the transfer of data over a variety of

high speed serial links including SMPTE 292, SMPTE 259, and

DVB-ASI video applications. The signaling rate can be anywhere

in the range of 195 to 1500 MBaud for each serial link. Each

channel operates independently with its own reference clock

allowing different rates. Each transmit channel accepts parallel

characters in an input register, encodes each character for

transport, and then converts it to serial data. Each receive

channel accepts serial data and converts it to parallel data,

decodes the data into characters, and presents these characters

to an output register. The received serial data can also be

reclocked and retransmitted through the serial outputs.

illustrates typical connections between independent video

coprocessors and corresponding CYV15G0404DXB chips.

Synchronous LVTTL parallel interface

JTAG boundary scan

Built In Self Test (BIST) for at-speed link testing

❐

Low power 3W at 3.3V typical

Single 3.3V supply

256 ball thermally enhanced BGA

0.25μ BiCMOS technology

JTAG device ID ‘0C811069’x

Link quality indicator by channel

Analog signal detect

Digital signal detect

•

Transceiver with Reclocker

San Jose

CYV15G0404DXB

Independent

Reclocker

Channel

CA 95134-1709

CYV15G0404DXB

Revised December 14, 2007

•

408-943-2600

Figure 1

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