cyv15g0404dxb Cypress Semiconductor Corporation., cyv15g0404dxb Datasheet - Page 11

• Manufacturer Part Number: cyv15g0404dxb
• Description: Independent Clock Quad Hotlink Ii Transceiver With Reclocker
• Manufacturer: Cypress Semiconductor Corporation.

Pin Definitions
CYV15G0404DXB Quad HOTLink II Transceiver
Document #: 38-02097 Rev. *B
LFIA
LFIB
LFIC
LFID
WREN
ADDR[3:0]
DATA[7:0]
RFMODE[A..D][1:0] Internal Latch
FRAMCHAR[A..D] Internal Latch
DECMODE[A..D]
DECBYP[A..D]
RXCKSEL[A..D]
RXRATE[A..D]
SDASEL[A..D][1:0] Internal Latch
ENCBYP[A..D]
TXCKSEL[A..D]
TXRATE[A..D]
RFEN[A..D]
RXPLLPD[A..D]
RXBIST[A..D]
TXBIST[A..D]
OE2[A..D]
OE1[A..D]
PABRST[A..D]
GLEN[11..0]
FGLEN[2..0]
Note
6. See
Name
Device Configuration and Control Bus Signals
Internal Device Configuration Latches
Device Configuration and Control Interface
Internal Latch
LVTTL Output,
asynchronous
LVTTL input,
asynchronous,
internal pull up
LVTTL input
asynchronous,
internal pull up
LVTTL input
asynchronous,
internal pull up
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
Internal Latch
I/O Characteristics
(continued)
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for detailed information on the internal latches.
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of five internal conditions. LFIx is asserted LOW when any of these condi-
tions are true:
■
■
■
■
■
■
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into the
latch specified by the address location on the ADDR[3:0] bus.
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET.
Control Data Bus. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
latches within the device, and the initialization value of the latches upon the assertion
of RESET.
Reframe Mode Select.
Framing Character Select.
Receiver Decoder Mode Select.
Receiver Decoder Bypass.
Receive Clock Select.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Transmit Encoder Bypass.
Transmit Clock Select.
Transmit PLL Clock Rate Select.
Reframe Enable.
Receive Channel Power Control.
Receive Bist Disabled.
Transmit Bist Disabled.
Differential Serial Output Driver 2 Enable.
Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer
Global Latch Enable.
Force Global Latch Enable.
Signal Description
Received serial data rate outside expected range
Analog amplitude below expected levels
Transition density lower than expected
Receive channel disabled
ULCx is LOW
No REFCLKx±.
Table 10
shows how the latches are mapped in the device.
Table 10
shows how the latches are mapped in the device.
Reset.
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Table 9
CYV15G0404DXB
lists the configuration
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Table 9
Page 11 of 44
lists the
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