sta323wtr STMicroelectronics, sta323wtr Datasheet - Page 29

• Manufacturer Part Number: sta323wtr
• Description: 2.1 High Efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA323W
5
Pin descriptions
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
The half-bridge PWM outputs 1A, 1B, 2A and 2B provide the inputs signals to the speakers.
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
Driving RESET low sets all outputs low and returns all register settings to their defaults. The
reset is asynchronous to the internal clock.
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
The SDA (I
(See
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
The phase locked loop power is applied here. This +3.3V supply must be well bypassed and
filtered for noise immunity. The audio performance of the device is critically dependent upon
the PLL circuit.
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
This is the master clock input required for the operation of the digital core. The master clock
must be an integer multiple of the LR clock frequency. Typically, the master clock frequency
is 12.288 MHz (256 * Fs) for a 48kHz sample rate, which is the default at power-up. Do not
over-clock the device (use a frequency higher than that recommended for the system clock)
otherwise it may not operate correctly or be able to communicate.
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
The PLL filter connects to external filter components for PLL loop compensation. Refer to
the schematic diagram
for the recommended circuit.
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
The serial or bit clock input is for framing each data bit. The bit clock frequency, using I
serial format, is typically 64 * Fs .
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
PCM audio information enters the device here. Six format choices are available including
I
OUT1A, 1B, 2A and 2B (Pins 16, 10, 9 and 3)
The left/right clock input is for data word framing. The clock frequency is at the input sample
rate Fs.
2
S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
Chapter 6 on page
2
C Data) and SCL (I
Figure 9: Power schematic for 1 mono parallel channel on page 11
30.) Fast-mode (400 kB/sec.) I
2
C Clock) pins operate according to the I
2
C communication is supported.
2
C specification
Pin descriptions
2
29/71
S