hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 21

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
3 - 0
7 - 0
7 - 6
4 - 0
7 - 0
7 - 0
BIT
BIT
BIT
BIT
BIT
7
6
5
4
5
Software Reset
Black Screen
Line LOCKED Flag
Standard Error Flag This flag when set (‘1’) indicates that the Standard detected does not match the one se-
Not Used
Reserved
Reserved
Lost HSYNC
Control (SNAP Bit)
Reserved
Reserved
Product ID Code
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
TABLE 29. SOFTWARE RESET AND VIDEO STATUS REGISTER
When this bit is set to 1, the entire device except the I
exactly like the RESET input. The software reset will initialize all register bits to their reset
state. Once set this bit is self clearing after only 4 CLK periods. This bit is cleared on pow-
er-up by the external RESET pin.
This flag when set (‘1’) will set the output video to black when a lost vertical sync has
been detect. This flag is cleared after a RESET.
This flag when set (‘1’) indicates that the Line Locked-Phase Locked Loop has locked to
the video data. This flag is read only and cleared after a RESET or Software Reset.
lected in the Video Input Control Register. The standard is checked against a line count
and if the line count is significantly different than the expected value then this flag is trig-
gered. This flag is read only and cleared after a RESET or Software Reset.
Write ignored, Read 0’s.
This register is reserved. This register will read all zero’s and is write ignored.
This register is reserved. This register will read all zero’s and is write ignored.
This bit controls when the PLL will declare lost horizontal sync, leave track mode and re-
turn to acquisition to acquire a new HSYNC reference. When this bit is cleared, lost line
lock is declared after 12 missing horizontal syncs. When this bit is set, lost line lock is
declared after one missing horizontal sync. This bit is cleared by RESET.
This register is reserved. This register will read all zero’s and is write ignored.
This register is reserved. This register will read all zero’s and is write ignored.
This register contains the last two digits of the product part number for use as a software
ID. These bits are read only and always read 0x12.
TABLE 33. PRODUCT ID REGISTER
TABLE 32. RESERVED
TABLE 30. RESERVED
TABLE 31. RESERVED
SUB ADDRESS = 0x1A
SUB ADDRESS = 0x1B
SUB ADDRESS = 0x17
SUB ADDRESS = 0x18
SUB ADDRESS = 0x19
HMP8112A
4-21
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
2
C bus is reset to a known state
0000 0000
0000 0000
0001 0010
0 0000
RESET
STATE
RESET
STATE
RESET
STATE
RESET
STATE
RESET
STATE
0000
(0x12)
00
0
0
0
0
0
B
B
B
B
B
B
B
B
B
B
B