hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 7

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

For PAL systems there are 283.75 cycles of chrominance
per line. Chrominance information is spaced at quarter line
intervals with a reference phase of 135
phase alternates from line to line by 90
the PAL chrominance and luminance signals the user select-
able filters should be enabled. The chroma notch filter built
into the luminance channel should be enabled for PAL sys-
tems to reduce cross luminance effects. The low pass filter in
the chrominance processing chain helps to reduce cross
color products.
The demodulator in the decoder decodes the color compo-
nents into U and V. The U and V components are converted
to Cb and Cr components after the decoding process.
YCbCr has a usable data range as shown in Figure 7. The
data range for Y is limited to a minimum of 16.
AMPLITUDE
AMPLITUDE
AMPLITUDE
AMPLITUDE
FIGURE 5. COMPOSITE NTSC INTERLEAVE SCHEME
FIGURE 6. COMPOSITE PAL INTERLEAVE SCHEME
Y
Y
Y
Y
f
H
/4
I, Q
I, Q
f
FREQUENCY
H
FREQUENCY
FREQUENCY
FREQUENCY
/2
I, Q
I, Q
f
f
H
H
f
o
I, Q
I, Q
H
. To fully separate
/2
o
f
. The reference
H
/4
Y
Y
Y
Y
HMP8112A
4-7
The decoder is compatible with all NTSC and PAL video for-
mats available throughout the world. Table 2 shows the com-
patible video standards.
Horizontal Sync Detection
Horizontal sync is detected in the Output Sample Rate con-
verter (OSR). The OSR spatially aligns the pixels in the verti-
cal direction by using the horizontal sync information
embedded in the digital video data stream. The HSYNC
sync pulse out of the decoder is a video synchronous output
pin. This signal follows the horizontal sync of an input video
source. If there is no source the HSYNC pin will continue to
run at video rates due to the Line Locked PLL free-running.
HSYNC can be moved throughout the video line using the
HSYNC Start and End time registers. This 10-bit register
allows the HSYNC to be moved in OSR clock increments
(12.27MHZ, 13.5MHz or 14.75MHz).
Vertical Sync and Field Detection
The vertical sync and field detect circuit of the decoder uses
a low time counter to detect the vertical sync sequence in
the video data stream. The low time counter accumulates
the low time encounted after the horizontal sync edge or at
the start of each line. When the low time count exceeds the
vertical sync detect threshold, VSYNC is asserted immedi-
ately. VSYNC will remain asserted for a minimum of 1 line.
The FIELD flag is updated at the same time as the VSYNC
line. The FIELD pin is a ‘0’ for ODD fields and a ‘1’ for even
fields.
In the case of lost vertical sync or excessive noise that would
prevent the detection of vertical sync, the FIELD flag will
continue to toggle. Lost vertical sync is declared if after 337
lines a vertical sync period was not detected for 3 successive
lines. When this occurs the phase locked loops are initialized
to the acquisition state.
The VSYNC pulse out of the decoder follows the vertical
sync detection and is typically 6.5 lines long. The VSYNC
will run at the field rate of the selected video standard
selected. For NTSC the field rate is 60Hz and for PAL the
field rate is 50Hz. This signal will continue to run even in the
event of no incoming video signal.
255
248
128
16
Y DATA
RANGE
WHITE
BLACK
FIGURE 7. YCbCr DATA RANGES
100%
255
240
212
128
44
16
0
Cb DATA
RANGE
YELLOW
YELLOW
BLUE
BLUE
100%
75%
100%
75%
255
240
212
128
44
16
0
Cr DATA
RANGE
CYAN
CYAN
100%
100%
75%
RED
75%
RED