hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 23

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

Pin Description
CCLAMP_CAP
LCLAMP_CAP
GAIN_CTRL
LAGC_CAP
L_ADIN
DEC_T
RESET
DEC_L
L_OUT
NAME
WPE
LIN0
LIN1
LIN2
SDA
SCL
CLK
CIN
PQFP PIN
NUMBER
13, 38
19
27
28
78
30
77
76
29
40
41
34
7
6
5
8
9
OUTPUT
INPUT/
Output
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Composite video input. This input must be AC-coupled to the video signal using a
1.0 PF capacitor and terminated with a 75-ohm resistor. These components should
be as close to this pin as possible for best performance. If not used, this pin should
be connected to AGND thru a 0.1 PF capacitor.
Composite video input. This input must be AC-coupled to the video signal using a
1.0 PF capacitor and terminated with a 75-ohm resistor. These components should
be as close to this pin as possible for best performance. If not used, this pin should
be connected to AGND thru a 0.1 PF capacitor.
Composite video or Luminance (Y) video input. This input must be AC-coupled to the
video signal using a 1.0 PF capacitor and terminated with a 75-ohm resistor. These
components should be as close to this pin as possible for best performance. If not
used, this pin should be connected to AGND thru a 0.1 PF capacitor.
Chrominance (C) video Input. This input must be AC-coupled to the video signal us-
ing a 1.0 PF capacitor and terminated with a 75-ohm resistor. These components,
and corresponding anti-aliasing low-pass filter, should be as close to this pin as pos-
sible for best performance. If not used, this pin should be connected to AGND thru a
0.1 PF capacitor.
White Peak Enable. When enabled (‘1’), the video amplifiers gain is reduced when
the digital output code exceeds 248. When disabled (‘0’) the video amplifier will clip
when the A/D reaches code 255.
Gain Control Input. DC voltage to set the S-Video CIN chrominance video amplifier’s
gain. Reference Figure 3 for gain control curve.
Decoupling for upper A/D Converter Reference. Recommend connecting 0.1 PF and
0.01PF ceramic capacitors in parallel to AGND.
Decoupling for lower A/D Converter Reference. Recommend connecting 0.1 PF and
0.01PF ceramic capacitors in parallel to AGND.
Capacitor Connection for Luminance AGC Circuit. Controls the AGC loop time con-
stant. Recommend connecting a 0.01 PF ceramic capacitor to AGND.
Capacitor Connection for Luminance Clamp Circuit. Controls the clamp loop time
constant. Recommend connecting a 0.047 PF ceramic capacitor to AGND.
Capacitor Connection for Chrominance Clamp Circuit. Controls the clamp loop time
constant. Recommend connecting a 0.047 PF ceramic capacitor to AGND.
Luminance A/D Converter input from external anti-alias filter. Reference Figure 1.
Analog output of the video multiplexer. This output should connect to an external
anti-alias filter and return to L_ADIN input. Reference Figure 1.
The serial I
The serial I
Master clock for the decoder. This clock is used to run the internal logic, A/D convert-
ers, and Phase Locked Loops. All I/O pins (except the I
master clock. A ±50ppm crystal should be used with a waveform symmetry of
60/40% or better.
Asynchronous Reset pin. Master Chip reset to initialize the internal states and set
the internal registers to a known state.
HMP8112A
2
2
C serial input/output data line.
C serial bus clock line.
4-23
DESCRIPTION
2
C) are synchronous to this