mt24d836m-xx Micron Semiconductor Products, mt24d836m-xx Datasheet - Page 2

• Manufacturer Part Number: mt24d836m-xx
• Description: Dram Module
• Manufacturer: Micron Semiconductor Products

OBSOLETE
FAST PAGE MODE
tions (READ or WRITE) within a row-address-defined (A0 -
A10) page boundary. The FAST PAGE MODE cycle is
always initiated with a row address strobed-in by RAS#
followed by a column address strobed-in by CAS#. CAS#
may be toggled-in by holding RAS# LOW and strobing-in
different column addresses, thus executing faster memory
cycles. Returning RAS# HIGH terminates the FAST PAGE
MODE operation.
REFRESH
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
A0-A10
CAS0#
RAS0#
CAS1#
CAS2#
RAS2#
CAS3#
FAST PAGE MODE operations allow faster data opera-
Returning RAS# and CAS# HIGH terminates a memory
WE#
V
V
CC
SS
WE#
CAS#
RAS#
OE#
WE#
CAS#
RAS#
OE#
DQ19
DQ1
DQ1-4
DQ1-4
11
11
A0-A10
A0-A10
U1
U3
U1-U12
U1-U12
WE#
CAS#
RAS#
OE#
WE#
CAS#
RAS#
OE#
FUNCTIONAL BLOCK DIAGRAM
DQ1-4
DQ1-4
11
11
A0-A10
A0-A10
U2
U4
MT12D436 (16MB)
WE#
CAS#
RAS#
WE#
CAS#
RAS#
D
D
DQ27
DQ9
11
11
A0-A10
A0-A10
2
U11
Q
U9
Q
the RAS# HIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#
ONLY, CBR or HIDDEN) so that all 2,048 combinations of
RAS# addresses (A 0 -A10) are executed at least every 32ms,
regardless of sequence. The CBR REFRESH cycle will in-
voke the refresh counter for automatic RAS# addressing.
x18 CONFIGURATION
pins must be connected together (DQ1 to DQ19, DQ2
to DQ20 and so forth, and CAS0# to CAS2# and CAS1# to
CAS3#). Each RAS# is then a bank select for the x18 memory
organization.
For x18 applications, the corresponding DQ and CAS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ10
WE#
CAS#
RAS#
OE#
WE#
CAS#
RAS#
OE#
DQ28
DQ1-4
DQ1-4
11
11
A0-A10
A0-A10
U5
U7
PARITY DRAM SIMMs
WE#
CAS#
RAS#
OE#
WE#
CAS#
RAS#
OE#
DQ1-4
DQ1-4
U9-U12 = 4 Meg x 1 DRAMs
11
11
U1-U8 = 4 Meg x 4 DRAMs
A0-A10
A0-A10
4, 8 MEG x 36
U6
U8
„1997, Micron Technology, Inc.
WE#
CAS#
RAS#
WE#
CAS#
RAS#
D
D
DQ18
DQ36
11
11
A0-A10
A0-A10
U10
U12
Q
Q