pxb4340e Infineon Technologies Corporation, pxb4340e Datasheet - Page 112

• Manufacturer Part Number: pxb4340e
• Description: Atm Oam Processor Aop
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Bit 31
Bit 30..15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
PAR
Dword parity protection. In normal operation write to 0. Should always
read as 0.
Initialize to 0 at connection setup. Do not change by µP in normal
operation.
CICCEN
1
CSCCTEN
1
CECCTEN
1
CSCCOEN
1
Reserved, set to 0.
CRDIMEN
0
1
CAISMEN
0
1
Enable Internal Continuity Check, terminating ICC in
downstream direction. Set to 0 if ICC is not used.
Terminate a F5 Segment Continuity Check.
Should only be enabled at a F5 TSP (CTSP=1).
Terminate a F5 End-to-End Continuity Check Flow.
Should only be enabled at a F5 TEP (CIP=0).
Originate a F5 Segment Continuity Check Flow.
Should only be enabled at a F5 OSP (COSP=1).
F5 RDI monitoring disabled.
F5 RDI monitoring enabled.
State transition to ASI failure state and out of ASI failure
state is reported by use of the µP interrupt DCSTTR.
F5 AIS monitoring disabled.
F5 AIS monitoring enabled.
State transition to AIS failure state and out of AIS failure
state is reported by use of the µP interrupt DCSTTR.
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