pxb4340e Infineon Technologies Corporation, pxb4340e Datasheet - Page 139
pxb4340e
Manufacturer Part Number
pxb4340e
Description
Atm Oam Processor Aop
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXB4340E.pdf
(185 pages)
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The AOP uses external, synchronous, static RAM (SSRAM) for the storage of connection
related OAM data. Two identical SSRAM interfaces are provided, one for each direction. The
SSRAM chips are operated with the system clock of up to 52 MHz.
All memory entries are protected with a parity bit at the MSB location.
The size of the SSRAM is depending on the number of supported connections: 8 dwords of 32-
bit are required per connection. Using SSRAM devices of 1 Mbit or 2 Mbit size, i.e. 32 K x 32 bit
and 64 K x 32 bit, respectively, the possible memory configurations are:
• 2 x 2 Mbit or 4 x 1 Mbit SSRAM for 16384 connections
• 1 x 2 Mbit or 2 x 1 Mbit SSRAM for 8192 connections
• 1 x 1 Mbit SSRAM for 4096 connections
These are the values for one direction. Both up- and downstream external memory should
always be configured symmetrical. The selection 1 Mbit or 2 Mbit SSRAM chips is done via
register bits.
Data Sheet
shows an example of maximum RAM size with four 1 Mbit devices.
x = U for upstream, D for downstream RAM
SYSCLK
shows an example of maximum RAM size with two 2 Mbit devices,
RCE1x
RCE0x
RSCx
RCE3x
RADRx(14:0)
RADVx
ROEx
RGWx
RDATx(31:0)
+3.3 V
+3.3 V
+3.3 V
GND
GND
10 k
10 k
10 k
226
1 k
5-139
IO(31:0)
A(15)
A(14:0)
A DV
OE
GW
CLK
CE of RAM No. 0
ADSC
BWE
CE2
CE2
BW1
BW2
MODE
ZZ
ADSP
BW3
BW4
CE of RAM No. 1
2x2M configuration
0
1
04.2000
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