peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 146
peb3456
Manufacturer Part Number
peb3456
Description
Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456.pdf
(424 pages)
- Current page: 146 of 424
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A1
LBE
EMI
4.13.2.5 Mailbox Interrupts
•
The ’Mailbox’ interrupt vector is generated, in case that the host CPU on PCI side has
written data to the mailbox status register MBP2E0. The bit field STATUS contains a
copy of MBE2P0.MB(6:0).
Test Unit Interrupts Type 0
•
OOS
A0
Data Sheet
LAST
LAST
15
15
14
14
0
0
13
0
Receiver Out Of Synchronization
The ’Receiver Out of Synchronization’ interrupt vector is generated
whenever the test unit detects a change in synchronization. The actual
state of the receiver is shown in TURSTAT.OOS.
Input all ‘0’s
The ‘Input all ‘0’s’ interrupt vector is generated whenever the TE3-
CHATT detects 32 continuous ‘0’s or when this consition is resolved.
The actual state is shown in TURSTAT.A0.
Input all ‘1’s
The ‘Input all ‘1’s’ interrupt vector is generated whenever the TE3-
CHATT detects 32 continuous ‘1’s or when this consition is resolved.
The actual state is shown in TURSTAT.A1.
Latched Bit Error Detected Flag
The ’Latched Bit Error Detected Flag’ interrupt vector is generated with
the first occurance of a bit error.
End of Measurement Interval
The ‘End of Measurement Interval’ interrupt vector is generated when
the end of the programmed measurement interval is reached.
0
EMI
11
STATUS(6:0)
LBE
10
A1
9
A0
8
146
OOS
7
7
6
6
10
11
B
B
5
5
4
4
Functional Description
01000
00000
PEB 3456 E
H
B
05.2001
0
0
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