peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 173
![no-image](/images/no-image-200.jpg)
peb3456
Manufacturer Part Number
peb3456
Description
Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456.pdf
(424 pages)
- Current page: 173 of 424
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CONF2
CONF3
RBAFT
Interrupt control PCI bus side
IQIA
IQBA
IQBL
IQMASK
GISTA/GIACK
GMASK
Channel specification registers (* = CSPEC)
*_CMD
*_MODE_REC
*_REC_ACCM
*_MODE_XMIT
*_XMIT_ACCM
*_BUFFER
*_FRDA
8.1.2
This section shows all registers which are located on the first configuration bus. These
registers are used to setup the basic operating modes of the device and to setup the port,
time slots and channels. System software has access to these registers via the PCI bus.
Table 8-2
Register
General Control
CONF1
SFDT
Data Sheet
PCI Slave Register Set (Direct Access)
PCI Slave Register Set
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
0EC
04C
0E0
0E4
0E8
0F0
0F4
040
044
048
050
000
004
008
014
018
020
024
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
FFFFFFFF
00000000
00090000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00200000
00000000
Reset
value
173
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Receiver ACCM Map
Mode Transmit
Transmit ACCM Map
Buffer Configuration
First Receive Descriptor
Addr.
Comment
Configuration Register 1
Configuration Register 2
Configuration Register 3
Receive Buffer Access Failed
Interrupt Threshold
Small Frame Dropped
Interrupt Threshold Register
Interrupt Queue Initialization
Interrupt Queue Base Addr.
Interrupt Queue Length
Interrupt Queue Mask
Global Interrupt Status/
Global Interrupt
Acknowledge
Interrupt Mask
Command
Mode Receive
Register Description
PEB 3456 E
05.2001
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