peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 382
peb3456
Manufacturer Part Number
peb3456
Description
Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456.pdf
(424 pages)
- Current page: 382 of 424
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CRC1
CRC Status Counter 1
Access
Address
Reset Value
CRC1
Data Sheet
15
: read
: 0F
: 0000
CRC1 counter
The S
received bit sequences 0001
specified in register VCRC in every submultiframe on a selectable S
In the primary rate access digital section CRC errors are reported from
the TE via S
synchronous state.
The counter is increased with every received bit error indication if
enabled in register RCR2. The counter will not be incremented once it
reaches FFFF
H
H
a
-bit error indication counter CRC1 (16 bits) counts either the
H
a6
. A read will clear this counter.
. Incrementing is only possible in the multiframe
CRCS1(15:0)
382
B
and 0011
B
or user programmable values
Register Description
PEB 3456 E
05.2001
a
0
-bit.
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