peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 71

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

(erroneous programming), no action will take place. Nevertheless, the CPU always has
to issue a ’Transmit Hold Reset’ command when it removes the HOLD bit in a descriptor,
no matter the data management unit has already seen the HOLD bit or not.
4.3.6
The TE3-CHATT operates per default as a little endian device. To support integration
into big endian environments, the data management unit provides an internal byte
swapping mechanism, which can be enabled via bit CONF1.LBE.
The big endian swapping applies only to the data section pointed to by the receive and
transmit descriptors in the shared memory.
Note: Byte swapping only effects the organization of packet data in system memory. All
If the HOLD bit is detected in a descriptor and the frame end bit is not set, the data
management unit will transfer all data of the belonging data section to the transmit buffer.
Afterwards it generates a ’Hold Caused Transmit Abort’ interrupt vector in order to inform
the host CPU about the erroneous descriptor structure. In PPP and HDLC mode the
abort status is propagated to the transmit buffer and the protocol machine, so that a abort
sequence is sent on the serial side. In TMA mode the data management unit generates
a ’Hold Caused Transmit Abort’ interrupt vector every time it recognizes the HOLD bit.
Then it reads the transmit descriptor once more. If the HOLD bit is removed it branches
to the next transmit descriptor and proceeds with normal operation. Otherwise, when the
HOLD bit is still set, the channel is suspended for further operation and an internal poll
bit is set. Following requests from the transmit buffer will not be served, but the number
of requested data is stored in the open request register.
The host CPU can remove the hold condition, when the next transmit descriptor is
available in system memory. Therefore the CPU has to execute a ’Transmit Hold Reset’
command, which will reactive the channel. When the transmit buffer requests a new data
transfer or when open request are stored in the on-chip database the data management
unit repolls the transmit descriptor and checks the HOLD bit again. If the HOLD bit is
removed it branches to next transmit descriptor.
If the CPU issues a ’Transmit Hold Reset’ command and does not remove the HOLD bit
Data Sheet
internal registers, as well as the descriptors, address pointers or interrupt vectors
are handled with little endian byte ordering.
Byte Swapping
71
Functional Description
PEB 3456 E
05.2001