sta559bwqs STMicroelectronics, sta559bwqs Datasheet
sta559bwqs
Available stocks
Related parts for sta559bwqs
sta559bwqs Summary of contents
Page 1
... Provides improved audio image width, – Synthesizes a 3-D stereo soundfield ! PowerSSO-36 slug down package Temp range, °C PowerSSO-36 slug down PowerSSO-36 slug down Rev 1 STA559BWQS with QSound QHD PowerSSO-36 slug down 2 S input data interface ® enhancement technology seperation and depth for stereo signals ...
Page 2
... Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STA559BWQS ...
Page 3
... STA559BWQS 4.4.4 4.4.5 4.4.6 5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 Configuration register A (addr 0x00 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.2 Configuration register B (addr 0x01 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3 Configuration register C (addr 0x02 5.3.1 5.3.2 5.3.3 5.4 Configuration register D (addr 0x03 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.5 Configuration register E (addr 0x04 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Thermal warning adjustment bypass ...
Page 4
... AutoMode register 2 (addr 0x0C interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STA559BWQS ...
Page 5
... STA559BWQS 5.12.1 5.12.2 5.12.3 5.12.4 5.12.5 5.12.6 5.12.7 5.12.8 5.12.9 5.12.10 Coefficient a1 data register bits 7.. 5.12.11 Coefficient a2 data register bits 23.. 5.12.12 Coefficient a2 data register bits 15.. 5.12.13 Coefficient a2 data register bits 7.. 5.12.14 Coefficient b0 data register bits 23.. 5.12.15 Coefficient b0 data register bits 15.. 5.12.16 Coefficient b0 Data Register Bits 7.. 5.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.12.18 User-defined 5.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.12.21 Over-current post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.13 Variable max power correction registers (addr 0x27 - 0x28 ...
Page 6
... Contents 10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 64 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6/66 STA559BWQS ...
Page 7
... STA559BWQS Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Thermal data Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Electrical specifications - power Section Table 8. Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. Register summary Table 10. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. Input sample rates and clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12 ...
Page 8
... Limiter release threshold as a function of LxRT bits (AC-Mode Table 67. Limiter attack threshold as a function of LxAT bits (DRC-mode Table 68. Limiter release threshold function of LxRT bits (DRC-mode).. . . . . . . . . . . . . . . 51 Table 69. RAM block for biquads, mixing, scaling, and bass management . . . . . . . . . . . . . . . . . . . . 57 Table 70. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8/66 STA559BWQS ...
Page 9
... STA559BWQS Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. Pin connection PowerSSO-36 (top view Figure 3. Test circuit Figure 4. Test circuit Figure 5. Output power vs supply voltage (R Figure 6. Output power vs. supply voltage (R Figure 7. Output power vs. supply voltage (R Figure 8. Output power vs. supply voltage (R Figure 9. Output power vs. supply voltage (R Figure 10 ...
Page 10
... W provided by the device and external ® power for DDX power drive. Also provided in the STA559BWQS are a full assortment of digital processing features. This includes programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. AutoModes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions, for instance, auto volume loudness, preset volume curves and preset EQ settings ...
Page 11
... STA559BWQS 1.3 Block diagram Figure 1. Block diagram interface DSP (Equalization, Tone, Volume, Bass) PLL Digital (DSP Protection current/thermal Power control DDX Regulators Description and block diagram Channel 1A Channel 1B Logic Channel 2A Channel 2B Bias Power 11/66 ...
Page 12
... OUT1B 10 VCC1 11 GND1 12 OUT1A 13 14 VDD 15 GND Type Name GND GND_SUB TEST_MODE I/O VSS I/O VCC_REG O OUT2B GND GND2 Power VCC2 O OUT2A STA559BWQS 36 VDD_DIG 35 GND_DIG 34 SCL 33 SDA 32 INT_LINE 31 RESET 30 SDI 29 LRCKI 28 BICKI 27 XTI 26 PLL_GND 25 FILTER_PLL VDD_PLL 24 PWRDN 23 GND_DIG 22 VDD_DIG 21 20 TWARN/OUT4B ...
Page 13
... STA559BWQS Table 2. Pin description (continued) Pin Connections diagram and pins description Type Name O OUT1B Power VCC1 GND GND1 I/O OUT1A GND GND_REG Power VDD I/O GND O OUT3B/DDX3B O OUT3A/DDX3A O EAPD/OUT4A I TWARN/OUT4B ...
Page 14
... Thermal data Symbol R Thermal resistance junction-ambient PowerSSO-36 th j-amb T Thermal shut-down junction temperature th-sdj T Thermal warning temperature th-w T Thermal shut-down hysteresis temperature th-sdh 1. See Chapter 7: Package thermal characteristics on page 61 14/66 Parameter (1) for details. STA559BWQS Min Typ Max Unit 24 °C/W 150 °C 130 °C 25 °C ...
Page 15
... STA559BWQS 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V Power supply voltage (VCC1, VCC2) cc Vdd Logic supply T Operating junction temperature op T Storage temperature stg Note: Stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ ...
Page 16
... (1) Resistive load ( load (1) Resistive load (1) Resistive load Power Down = 0 TRISTATE = 0 PCM input signal = -60 dBFS Switching frequency = 384 kHz No LC filters Internal clock = 49.152 MHz STA559BWQS Min Typ Max -10 10 -10 10 0.2 * VDD_DIG 0.8 * VDD_DIG 0.4 * VDD_DIG 0.8 * VDD_DIG -25 66 125 ...
Page 17
... STA559BWQS Table 7. Electrical specifications - power Section (continued) Symbol Parameter Ilim Overcurrent limit Isc Short circuit protection Under voltage protection UVL threshold t Output minimum pulse width min Output power BTL Output power SE Output power BTL Po Output power SE Output power BTL Output power SE ...
Page 18
... High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B DTout(A) Q1 Rload=4Ω OUTA L67 10µ Iout=1A Q3 C69 C71 470nF 470nF Duty cycle A and B: Fixed to have DC output current the direction shown in figure STA559BWQS IC status OUTxY Vcc (3/4)Vcc (1/2)Vcc (1/4)Vcc t DTr DTf R 8Ω + V67 = - ...
Page 19
... STA559BWQS 3.6 Electrical characteristics curves Figure 5. Output power vs supply voltage ( Ω) Po(W) 3 2.5 Rload = 2Ώ 1KHz 2 S.E. 1.5 1 THD=1% 500m 0 +4.5 +4.6 +4.7 +4.8 +4.9 +5 +5.1 +5.2 +5.3 +5.4 +5.5 +5.6 +5.7 +5.8 +5.9 Vcc(V) Figure 7. Output power vs. supply voltage ( Ω) Po(W) 3 2.5 Rload = 4Ώ 1KHz THD=10% 2 S.E. 1.5 1 500m 0 +4.5 +5 +5.5 +6 +6.5 +7 +7.5 Vcc (V) Figure 9. Output power vs. supply voltage ( Ω) ...
Page 20
... Eff(%) (Vcc = Figure 16. THD vs. frequency L THD% 1 0.5 0.2 0.1 0.05 0.02 0.01 20 2.5 3 3.5 4 STA559BWQS = 8 Ω) Rload = 8Ώ THD=10 1KHz BTL THD=1% +5.5 +6 +6.5 +7 +7.5 +8 +8.5 Vcc(V) (Vcc = out 4 Ω) Vcc = 5V Rload = 4Ώ 1KHz BTL 500m 1 1.5 2 2xPout (W) 8ohm Stereo DDX Mode Vcc=5V, Po= 1W ...
Page 21
... STA559BWQS Figure 17. PSSR +10 dBr +0 -10 Vcc = 5V - -30 -40 -50 -60 -70 -80 -90 -100 Frequency Hz Figure 19. Channel separation stereo S. Ω) mode (R L dBr A +10 +0 -10 -20 -30 -40 -50 -60 Stereo S.E. Mode Rl = 2Ώ,Vcc=5V - -80 -90 -100 20 50 100 200 500 Frequency (Hz) Figure 21 ...
Page 22
... Figure 26. FFT -60 dBFS stereo S.E. mode (R L dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 10k 20k STA559BWQS = 4 Ω) Stereo S.E. Mode Vcc=5V, Rl=4Ώ 1KHz 50 100 200 500 1k 2k Frequency (Hz Ω) Stereo S.E. Mode Vcc=5V, Rl=2Ώ 1KHz 50 100 200 500 1k 2k Frequency (Hz) L ...
Page 23
... Data input During the data input the STA559BWQS samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. ...
Page 24
... After receiving, the internal byte address the STA559BWQS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA559BWQS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...
Page 25
... STA559BWQS 4.4.5 Write mode sequence Figure 27. Write mode sequence BYTE DEV-ADDR WRITE START MULTIBYTE DEV-ADDR WRITE START 4.4.6 Read mode sequence Figure 28. Read mode sequence CURRENT DEV-ADDR ADDRESS READ START RANDOM DEV-ADDR ADDRESS READ START SEQUENTIAL DEV-ADDR CURRENT READ START SEQUENTIAL DEV-ADDR RANDOM ...
Page 26
... C1B6 C1B5 C1B4 C2B22 C2B21 C2B20 C2B14 C2B13 C2B12 C2B6 C2B5 C2B4 C3B22 C3B21 C3B20 C3B14 C3B13 C3B12 C3B6 C3B5 C3B4 STA559BWQS IR0 MCS2 MCS1 SAI3 SAI2 SAI1 CSZ1 CSZ0 OM1 PSL DSPB DEMP AME NSBW MPC BCLE IDE OCFG1 ...
Page 27
... The STA559BWQS will support sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock will be: " 32.768 MHz for 32 kHz " 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz " 49.152 MHz for 48Z kHz, 96 kHz, and 192 kHz ...
Page 28
... Bit RW 4..3 RW The STA559BWQS has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 13. ...
Page 29
... The on-chip STA559BWQS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the 3-state output (setting which directs the power output block to begin recovery), hold for period of time in the range of 0 ...
Page 30
... Serial data interface The STA559BWQS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA559BWQS always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 & ...
Page 31
... STA559BWQS Table 19. Support serial audio input formats for MSB-First (SAIFB = 0) (continued) BICKI Table 20. Supported serial audio input formats for LSB-First (SAIFB = 1) BICKI SAI [3:0] SAIFB 2 0000 16-23 bit data 0001 0 Left-Justified 16-24 bit data 0010 0 Right-Justified 24 bit data 0110 ...
Page 32
... Processing channel 1 receives right I 0: Processing channel 2 receives left I 1 C2IM 1: Processing channel 2 receives right can be mapped to any internal processing channel via the 2 S input channel to its corresponding processing STA559BWQS Interface format bit data bit data 2 ...
Page 33
... STA559BWQS 5.3 Configuration register C (addr 0x02 OCRB 1 5.3.1 DDX power output mode Table 23. DXX power output mode Bit The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. Table 24. Output modes ...
Page 34
... High-pass filter bypass Bit The STA559BWQS features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled. 5.4.2 De-emphasis Table 29. ...
Page 35
... STA559BWQS 5.4.3 DSP bypass Table 30. DSP bypass Bit Setting the DSPB bit bypasses the EQ functionality of the STA559BWQS. 5.4.4 Post-scale link Table 31. Post-scale link Bit Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster ...
Page 36
... Limiters act in anti-clipping mode 1: Limiters act in dynamic range compression mode RST Name Zero-detect mute enable: setting of 1 enables the 1 ZDE automatic zero-detect mute RST Name Miami-Mode enable: 0 MME 0: Sub mix into left/right disabled 1: Sub mix into left/right enabled STA559BWQS Description Description Description ...
Page 37
... STA559BWQS 5.5 Configuration register E (addr 0x04 SVE ZCE 1 1 5.5.1 Max power correction variable Table 36. Max power correction variable Bit 5.5.2 Max power correction Table 37. Max power correction Bit Setting the MPC bit turns on special processing that corrects the STA50x power device at high power ...
Page 38
... RST 3 RW STA559BWQS features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~ this mode, which is still greater than the SNR of AM radio. ...
Page 39
... STA559BWQS 5.5.8 Soft volume update enable Table 43. Soft volume update enable Bit RW RST 7 RW 5.6 Configuration register F (addr 0x05 EAPD PWDN 0 5.6.1 Output configuration Table 44. Output configuration Bit Table 45. Output configuration engine selection OCFG[1:0] 2 channel (full-bridge) power, 2 channel data-out: 1A/1B →1A/1B 2A/2B → 2A/2B 00 LineOut1 → ...
Page 40
... Bridge Half Bridge OUT2B OUT3A OUT3B Power Device EAPD RST Name Invalid input detect mute enable: setting of 1 enables 1 IDE the automatic invalid input detect mute STA559BWQS Half Bridge OUT1A Half Bridge OUT1B OUT2A Half Bridge Half Bridge OUT2B Channel 1 Channel 2 ...
Page 41
... STA559BWQS 5.6.3 Binary output mode clock loss detection Table 47. Binary output mode clock loss detection Bit Detects loss of input MCLK in binary mode and will output 50% duty cycle. 5.6.4 LRCK double trigger protection Table 48. LRCK double trigger protection Bit Actively prevents double trigger of LRCLK. ...
Page 42
... Line output fixed - no volume Line output variable - CH3 volume effects line output Line output variable with EQ - CH3 volume effects line output D5 D4 MV5 MV4 C1V5 C1V4 1 0 STA559BWQS Description C3M C2M C1M MV3 ...
Page 43
... C3V7 C3V6 0 1 The volume structure of the STA559BWQS consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5dB steps from + dB example if C3V = 00h or +48 dB and MV = 18h or –12 dB, then the total gain for channel 3 = +36 dB ...
Page 44
... Hard channel mute Hard channel mute AMGC1 AMGC2 0 0 User programmable clipping 2.1 AC limited clipping (10%) 2.1 DRC nighttime listening mode 2 XO1 XO0 AMAM2 STA559BWQS Volume +47 dB … +0 -0.5 dB … -59.5 dB -60 dB -61 dB -62 dB … -80 dB … Mode ...
Page 45
... STA559BWQS 5.8.3 AM interference frequency switching Table 56. AM interference frequency switching Bit Table 57. AutoMode AM switching frequency selection AMAM[2:0] 000 001 010 011 100 101 110 5.8.4 Bass management crossover Table 58. Bass management crossover Bit Table 59. Bass management crossover frequency ...
Page 46
... Bypass EQ on channel X 46/66 Crossover Frequency 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 C1LS1 C1LS0 C2LS1 C2LS0 C3LS1 C3LS0 STA559BWQS C1BO C1VPB C1EQBP C2BO C2VPB C2EQBP C3BO C3VPB C1TCB 0 D0 ...
Page 47
... STA559BWQS 5.9.3 Volume bypass Each channel contains an individual channel volume bypass particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel ...
Page 48
... D5 D4 L1A1 L1A0 L1AT1 L1AT0 L1RT3 L2A1 L2A0 1 0 STA559BWQS BTC3 BTC2 BTC1 Boost/cut -12 dB -12 dB … … +12 dB + L1R3 ...
Page 49
... The limiter attack thresholds are determined by the LxAT registers recommended in anti-clipping mode to set this to 0dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within STA559BWQS it is possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain ...
Page 50
... Table 64. LxR[3:0] Fast Slow Table 66. LxRT[3:0] 0 STA559BWQS Limiter release rate as a function of LxR bits. Release rate dB/ms 0000 0.5116 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0 ...
Page 51
... STA559BWQS Dynamic range compression mode Table 67. Limiter attack threshold as a function of LxAT bits (DRC- mode). LxAT[3:0] DRC (dB relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 5.12 User-defined coefficient control registers (addr 0x16 - 0x26) 5 ...
Page 52
... D4 C2B21 C2B20 C2B13 C2B12 C2B5 C2B4 C1B21 C1B20 C3B13 C3B12 STA559BWQS C1B11 C1B10 C1B9 C1B3 C1B2 C1B1 C2B19 C2B18 C2B17 C2B11 C2B10 ...
Page 53
... STA559BWQS 5.12.10 Coefficient a1 data register bits 7.. C3B7 C3B6 0 5.12.11 Coefficient a2 data register bits 23.. C4B23 C4B22 0 0 5.12.12 Coefficient a2 data register bits 15.. C4B15 C4B14 0 5.12.13 Coefficient a2 data register bits 7.. C4B7 C4B6 0 5.12.14 Coefficient b0 data register bits 23.. C5B23 C5B22 0 0 5.12.15 Coefficient b0 data register bits 15..8 ...
Page 54
... Coefficient write/read control register D7 D6 Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA559BWQS via RAM. Access to this RAM is available to the user via register interface. A collection of I²C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM ...
Page 55
... STA559BWQS will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. 5.12.18 User-defined EQ The STA559BWQS provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[ where Y[n] represents the output and X[n] represents the input ...
Page 56
... Pre-scale The STA559BWQS provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I and the bass-management ...
Page 57
... STA559BWQS Table 69. RAM block for biquads, mixing, scaling, and bass management Index (Decimal) Index (Hex … … 0x00 0x01 0x02 Channel 1 - Biquad 1 0x03 0x04 0x05 Channel 1 - Biquad 2 … ...
Page 58
... D5 D4 DCC13 DCC12 DCC5 DCC4 FDRC13 FDRC12 FDRC5 FDRC4 UVFAULT OVFAULT STA559BWQS MPCC11 MPCC10 MPCC9 MPCC3 MPCC2 MPCC1 DCC11 DCC10 DCC9 DCC3 ...
Page 59
... Application scheme for power supplies Figure 33 below shows a circuit diagram of a typical application for STA559BWQS.Particular care has to be given to the layout of the PCB, especially the power supplies. The 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This helps to prevent unwanted oscillation on the digital portion of the device due to inductive tracks of the PCB ...
Page 60
... STA559BWQS LEFT LEFT LEFT 470nF 470nF 470nF 470nF 470nF 470nF RIGHT RIGHT RIGHT ...
Page 61
... Package thermal characteristics Due to the high efficiency of the system the dissipated power is negligible, allowing the use of the STA559BWQS without heat sink but using only a small copper area on the PCB. Using a double layer PCB the thermal resistance junction to ambient with two copper ground ...
Page 62
... G LEAD COPLANARITY 0 STA559BWQS ® OUTLINE AND MECHANICAL DATA PowerSSO-36 (slug-down) hx45û BOTTOM VIEW 7587131 A ...
Page 63
... The feature requiring license is: QXpander (QHD ® QHD and QXpander obtained with the STA559BWQS via STMicroelectronics, please contact the HPC Audio Division Product Manager for details. Alternatively the license can be obtained directly from QSound Labs Inc. For details please contact: sales@qsound.com ...
Page 64
... Trademarks and other acknowledgements 10 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. QHD and QXpander are registered trademarks of QSound Labs Inc. 64/66 STA559BWQS ...
Page 65
... STA559BWQS 11 Revision history Table 70. Document revision history Date 28-Mar-2008 Revision 1 Initial release. Revision history Changes 65/66 ...
Page 66
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 66/ 66 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA559BWQS ...