tsp5071n STMicroelectronics, tsp5071n Datasheet - Page 10

• Manufacturer Part Number: tsp5071n
• Description: Programmable Codec/filter Combo 2nd Generation
• Manufacturer: STMicroelectronics

TS5070 - TS5071
This mode provides another stage of path verifica-
tion by enabling data written into the Receive PCM
Register to be read back from that register in any
Transmit time-slot at D
For Analog Loopback as well as for Digital Loop-
back PCM decoding continues and analog output
appears at VF
pro gramming ”No Output” in the Receive Gain
Register (see table 8).
INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface
Latches assume they are inputs, and therefore all
IL pins are in a high impedance state. Each IL pin
may be individually programmed as a logic input or
output by writing the appropriate instruction to the
LDR, see table 1 and 4. Bits L
writing the specific instruction to the LDR with the
L bits in the second byte set as specified in table 4.
Unused interface latches should be programmed
as outputs. For the TS5071, L5 should always be
programmed as an output.
Table 4: Byte 2 Function of Latch Direction Register
(*) State at power-on initilization.
Note: L5 should be programmed as an output for the TS5071.
Table 6: Byte 2 of Time-slot and Port Assignment Instructions
Notes:
1. The ”PS” bit MUST always be set to 0 for the TS5071.
2. T5 is the MSB of the time-slot assignment.
(*) State at power-on initialization
10/32
EN
0
7
1
1
L0
7
(note 1)
PS
L1
X
6
6
0
1
L
N
0
1
Bit
R
L2
(note 2)
5
Assign One Binary Coded Time-slot from 0–63
Assign One Binary Coded Time-slot from 0–63
Assign One Binary Coded Time-slot from 0–63
Assign One Binary Coded Time-slot from 0–63
O. The output can be disabled by
T5
X
5
Bit Number
L3
4
X
0 or D
T4
Bit Number
X
4
L4
3
X
5
1.
-L
IL Direction
L5
0
T3
2
X
3
Output
Input
must be set by
*
X
1
T2
2
X
X
0
T1
X
1
INTERFACE LATCH STATES
Interface Latches configured as outputs assume
the state determined by the appropriate data bit in
the 2-byte instruction written to the Latch Content
Register (ILR) as shown in tables 1 and 5.
Latches configured as inputs will sense the state
applied by an external source, such as the Off-
Hook detect output of a SLIC. All bits of the ILR,
i.e. sensed inputs and the programmed state of
outputs, can be read back in the 2nd byte of a
READ from the ILR. It is recommended that, dur-
ing initialization, the state of IL pins to be config-
ured as outputs should first be programmed, fol-
lowed immediately by the Latch Direction
Register.
Table 5: Interface Latch Data Bit Order
TIME-SLOT ASSIGNMENT
COMBO IIG can operate in either fixed time-slot or
time-slot assignment mode for selecting the Trans-
mit and Receive PCM time-slots. Following power-
on, the deviceis automaticallyin Non-Delayed Tim-
ing mode, in which the time-slot always begins with
the leading (rising) edge of frame sync inputs FS
and FS
with Delayed Data timing : see figure 6. FS
FS
other in BCLK period increments.
D0
T0
7
R
0
X
may have any phase relationship with each
R
D1
. Time-Slot Assignment may only be used
6
Disable D
Disable D
Enable D
(Transmit instruction)
Enable D
(Receive Instruction)
Enable D
(Transmit instruction)
Enable D
(Receive Instruction)
D2
5
X
R
X
R
X
R
0 Output, Disable D
0 Input, Disable D
1 Output, Disable D
1 Input, Disable D
Outputs (transmit instruction) *
Inputs (receive instruction) *
Bit Number
D3
4
Function
D4
3
D5
2
R
R
1 Input
0 Input
X
X
1 Output
0 Output
1
X
X
X
0
and
X