at25dq321a ATMEL Corporation, at25dq321a Datasheet - Page 10
at25dq321a
Manufacturer Part Number
at25dq321a
Description
32-megabit 2.7-volt Minimum Spi Serial Flash Memory With Dual-i/o And Quad-i/o Support
Manufacturer
ATMEL Corporation
Datasheet
1.AT25DQ321A.pdf
(61 pages)
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After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a
byte first. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back
at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array
to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-1.
Figure 7-2.
Figure 7-3.
AT25DQ321A [Preliminary]
SCK
SCK
SCK
SO
CS
SO
SO
CS
CS
SI
SI
SI
Read Array – 1Bh Opcode
Read Array – 0Bh Opcode
Read Array – 03h Opcode
8718A–DFLASH–04/10
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