at25dq321a ATMEL Corporation, at25dq321a Datasheet - Page 45

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at25dq321a

Manufacturer Part Number
at25dq321a
Description
32-megabit 2.7-volt Minimum Spi Serial Flash Memory With Dual-i/o And Quad-i/o Support
Manufacturer
ATMEL Corporation
Datasheet

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AT25DQ321A [Preliminary]
Figure 12-1. Reset
CS
SCK
SI
SO
12.2
Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query and identify the
device while it is in system. The identification method and the command opcode comply with the JEDEC standard
for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The
type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor
specific Device ID, and the vendor specific Extended Device Information.
The Read Manufacturer and Device ID command is limited to a maximum clock frequency of f
. Since not all
CLK
Flash devices are capable of operating at very high clock frequencies, applications should be designed to read the
identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used
in the application can be identified properly. Once the identification process is complete, the application can then
increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher
clock frequencies.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into
the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO
pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two
bytes of Device ID information. The fourth byte output will be the Extended Device Information (EDI) String Length,
which will be 01h indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin
will go into a high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data
will be output. As indicated in the JEDEC standard, reading the EDI String Length and any subsequent data is
optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be
read.
45
8718A–DFLASH–04/10

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