at88sa100s ATMEL Corporation, at88sa100s Datasheet - Page 10

• Manufacturer Part Number: at88sa100s
• Description: Battery Authentication Chip
• Manufacturer: ATMEL Corporation

3.2.
3.3.
3.4.
10
IO Blocks
Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the
following way:
IO Flow
The general IO flow for a MAC command is as follows:
3.
4.
5.
6.
7.
8.
9.
10. System waits t
11. System sends Transmit Flag.
12. Receive output block from the device, system checks CRC.
13. If CRC from the device is incorrect, indication transmission error, system resends Transmit flag.
14. System sends sleep flag to the device.
All commands other than MAC have a short execution delay. In these cases the system should omit steps 6, 7 & 8 and
replace this with a wait of duration t
Synchronization
Because the communications protocol is half duplex, there is the possibility that the system and the device will fall out
of synchronization with each other. In order to speed recovery, the device implements a timeout that forces the device
to sleep. See Section 2.6.1.
AT88SA100S [Preliminary]
Byte
Number
0
1 to (N-2) Packet
N-1, N
System sends wake token.
System sends Transmit Flag.
Receive 0x11 value from the device to verify proper wakeup synchronization.
System sends Command Flag.
System sends command block.
System waits t
System sends Transmit Flag. If command format is OK, the device ignores this flag because the computation
engine is busy. If there was an error, the device responds with an error code.
Name
Count
Checksum
PARSE
EXEC
, Refer to
for the device to check for command formation errors.
Meaning
Number of bytes to be transferred to the chip in the block, including count, packet and
checksum, so this byte should always have a value of (N+1). The maximum size block is
39 and the minimum size block is 4. Values outside this range will cause unpredictable
operation.
Command, parameters and data, or response. Refer to Section 4 for more details.
CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the
initial register value should be 0 and after the last bit of the count and packet have been
transmitted the internal CRC register should have a value that matches that in the block.
The first byte transmitted (N-1) is the least significant byte of the CRC value so the last
byte of the block is the most significant byte of the CRC.
3.1.1.
PARSE
+ t
EXEC
.
8558B–SMEM–09/09