at88sa100s ATMEL Corporation, at88sa100s Datasheet - Page 4

• Manufacturer Part Number: at88sa100s
• Description: Battery Authentication Chip
• Manufacturer: ATMEL Corporation

1.5.
2.
2.1.
4
Throughout this document, the complete message processed by the SA100S chip is documented. According to the
above specification, this always includes a single bit of ‘1’ pad after the message, followed by a 64 bit value
representing the total number of bits being hashed (less pad and length). If the length is less than 447 (512-64-1) then
the necessary number of ‘0’ bits are included between the ‘1’ pad and ‘length’ to stretch the last message block out to
512 bits.
When using standard libraries to calculate the SHA-256 digest, these pad and length bits should probably not be
passed to the library as most standard software implementations of the algorithm add them in automatically.
Security Features
This chip incorporates a number of physical security features designed to protect the key from unauthorized release.
These include an active shield over the entire surface of the internal memory encryption, internal clock generation,
glitch protection, voltage tamper detection and other physical design features.
Both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two
signals.
IO Protocol
Communications to and from this chip take place over a single asynchronously timed wire using a pulse count scheme.
The overall communications structure is a hierarchy:
Table 2.
IO Tokens
There are a number of IO tokens that may be transmitted along the bus:
The waveforms are the same in either direction, however there are some differences in timing based on the
expectation that the host has a very accurate and consistent clock while the device has significant variation in its
internal clock generator due to normal manufacturing and environmental fluctuations.
The bit timings are designed to permit a standard UART running at 230.4K baud to transmit and receive the tokens
efficiently. Each byte transmitted or received by the UART corresponds to a single bit received or transmitted by the
device. Refer to Applications Notes on Atmel’s website for more details describing how the UART should be controlled.
AT88SA100S [Preliminary]
Tokens
Flags
Blocks
Packets
Input: (To device)
Output: (From the device)
Wake
Zero
One
ZeroOut
OneOut
Implement a single data bit transmitted on the bus, or the wake-up event.
Comprised of eight tokens (bits) which convey the direction and meaning of the next group of bits (if any)
which may be transmitted.
of data follow the command and transmit flags. They incorporate both a byte count and a checksum to
ensure proper data transmission
of bytes form the core of the block without the count and CRC. They are either the input or output
parameters of a AT88SA100S chip command or status information from the AT88SA100S chip
IO Hierarchy
Wake device up from sleep (low power) state
Send a single bit from system to the device with a value of 0
Send a single bit from system to the device with a value of 1
Send a single bit from the device to the system with a value of 0
Send a single bit from the device to the system with a value of 1
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