is42s16800al-7tli Integrated Silicon Solution, Inc., is42s16800al-7tli Datasheet - Page 49

• Manufacturer Part Number: is42s16800al-7tli
• Description: 128-mbit Low-power Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY
09/18/03
COMMAND
INTERNAL
ADDRESS
CLOCK
INFORMATION
COMMAND
INTERNAL
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
DQ
READ
BANK a,
COL n
T0
Rev. 00A
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
Qn
T2
1-800-379-4774
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH; the
internal clock and related operation will resume on the
subsequent positive clock edge.
T3
T3
Qn+1
NOP
T4
D
NOP
IN
T4
n+1
NOP
T5
Qn+2
D
DON'T CARE
NOP
IN
T5
n+2
DON'T CARE
NOP
T6
Qn+3
ISSI
49
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