is42vm32200g Integrated Silicon Solution, Inc., is42vm32200g Datasheet - Page 10

• Manufacturer Part Number: is42vm32200g
• Description: 512k X 32bits X 4banks Low Power Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

CAS Latency
output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is
clocks, the data will be available by clock edge
1), and provided that the relevant access times are met, the data will be valid by clock edge
clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to
two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
Figure6: CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
COMMAND
COMMAND
CLK
DQ
CLK
DQ
T0
READ
T0
READ
CAS Latency=2
CAS Latency=3
T1
NOP
T1
NOP
tLZ
n +
tAC
m. The DQs will start driving as a result of the clock edge one cycle earlier
T2
NOP
tLZ
tAC
T2
NOP
Dout
tOH
T3
NOP
Dout
tOH
T3
DON’T CARE
UNDEFINED
T4
n +
m. For example, assuming that the
IS42VM32200G
(n + m
m
-
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