is42vm32200g Integrated Silicon Solution, Inc., is42vm32200g Datasheet - Page 11

• Manufacturer Part Number: is42vm32200g
• Description: 512k X 32bits X 4banks Low Power Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

Table4: Command Truth Table
Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A10 define OP CODE written to the mode register, and BA1/BA0 must be issued “0/0” in the mode register set, and “1/0”
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
Command Inhinit (NOP)
No Operation (NOP)
Mode Register Set
Extended Mode Register Set
Active (select bank and
activate row)
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Precharge Power Down Entry
Precharge Down Exit
Clock Suspend Entry
Clock Suspend Exit
Deep Power Down Entry
Deep Power Down Exit
H: High Level, L: Low Level, X: Don't Care, V: Valid
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
in the extended mode register set.
DQM Latency is 2 CLK.
assigned to the Deep Power Down function.
Function
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
CKEn
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
/CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
/RAS
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
X
X
X
X
V
X
X
/CAS
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
X
X
X
X
V
H
/WE
H
H
H
H
H
H
H
H
H
V
X
L
L
L
L
L
L
L
X
X
X
X
L
DQM
L/H
L/H
L/H
L/H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bank/Col
Bank/Col
Bank/Col
Bank/Col
ADDR
Bank
X
Bank/Row
OP CODE
OP CODE
IS42VM32200G
X
X
X
X
X
X
X
X
X
X
X
X
A10
H
H
H
L
L
L
Note
4
4
5
5
5
5
3
3
2
6
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