is42vm32200g Integrated Silicon Solution, Inc., is42vm32200g Datasheet - Page 3

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is42vm32200g

Manufacturer Part Number
is42vm32200g
Description
512k X 32bits X 4banks Low Power Synchronous Dram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

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Table2: Pin Descriptions
CLK
CKE
/CS
BA0~BA1
A0~A10
/RAS, /CAS, /WE
DQM0~DQM3
DQ0~DQ31
VDD/VSS
VDDQ/VSSQ
NC
Pin
System Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
Pin Name
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row Address
Column Address
Auto Precharge
RAS, CAS and WE define the operation.
Refer function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Multiplexed data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
: RA0~RA10
: CA0~CA7
: A10
Descriptions
IS42VM32200G
3

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