m34e02 STMicroelectronics, m34e02 Datasheet
m34e02
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m34e02 Summary of contents
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... Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40 Years’ Data Retention Packages – ECOPACK® (RoHS compliant) April 2006 2 Kbit Serial I²C Bus EEPROM with UFDFPN8 (MB) 2x3mm² (MLP) TSSOP8 (DW) 4.4x3mm² Rev 6 M34E02 1/33 www.st.com 1 ...
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... Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8.1 3.8.2 3.8.3 3.8.4 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Use within a DDR2 DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 Programming the M34E02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.1 2/33 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 17 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DDR2 DIMM isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ...
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... M34E02 5.1.2 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DDR2 DIMM inserted in the application mother board . . . . . . . . . . . . . 21 Contents 3/33 ...
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... DC characteristics Table 12. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 13. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4/33 M34E02 ...
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... M34E02 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. TSSOP and MLP connections (top view Figure 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Maximum R value versus bus parasitic capacitance (C) for Figure bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Result of setting the write protection Figure 7. Setting the write protection ( Figure 8 ...
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... Summary description The M34E02 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory ...
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... TSSOP and MLP connections (top view) 1. See the Package mechanical Table 1. Signal names E0, E1, E2 SDA SCL E0-E2 M34E02 SCL M34E02 SCL SDA AI09021 section for package dimensions, and how to identify pin-1. Chip Enable ...
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... V min but increases continuously), the CC CC has reached the Power On Reset CC tables). Once V has passed the POR threshold, the device is CC decreases continuously), as soon M34E02 operating voltage defined in CC voltage must drops CC ...
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... When Write Control (WC) is tied Low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register. indicates how the value of the pull-up resistor can be calculated). In voltage, when decoding an SWP or CWP instruction M34E02 M34E02 Signal description . (Figure 4 ...
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... SCL SDA 10/33 value versus bus parasitic capacitance (C) for 100kHz fc = 400kHz 100 C (pF) SDA SDA START Input Change Condition MSB MSB M34E02 2 C bus SDA MASTER SCL C 1000 STOP Condition ACK ACK STOP Condition ...
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... M34E02 Table 2. Device Select Code Memory Area Select (2) Code (two arrays) Set Write Protection (SWP) Clear Write Protection (CWP) Permanently Set Write Protection (PSWP) Read SWP Read CWP (2) Read PSWP 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. ...
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... For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. 12/ protocol. This is summarized in th clock pulse period, the receiver pulls Serial Data (SDA) Low to M34E02 Figure 5 Any device that sends ...
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... M34E02 3.5 Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2 The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “ ...
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... Setting the write-protection The M34E02 has a hardware write-protection feature, using the Write Control (WC) signal. This signal can be driven High or Low, and must be held constant for the whole instruction sequence. When Write Control (WC) is held High, the whole memory array (addresses 00h to FFh) is write protected ...
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... M34E02 3.7 Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10 bit” ...
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... Addressing the Memory NO DATA for the WRITE Operation Continue the WRITE Operation ACK ACK DATA IN ACK ACK DATA IN 1 DATA IN 2 AI01941 Send Address and Receive ACK START YES Condition DEVICE SELECT with Continue the Random READ Operation M34E02 AI01847C ...
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... M34E02 3.7.3 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t shown in Table 12, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master ...
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... For all Read commands, the device waits, after each byte read, for an acknowledgment th during the 9 bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. 18/33 Figure 10. M34E02 ...
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... M34E02 Figure 10. Read mode sequences CURRENT ADDRESS READ RANDOM ADDRESS READ SEQUENTIAL CURRENT READ SEQUENTIAL RANDOM READ 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 must be identical. ACK NO ACK DEV SEL DATA OUT R/W ACK ACK DEV SEL * ...
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... The device is delivered with all bits in the memory array set to ‘1’ (each Byte contains FFh). 5 Use within a DDR2 DIMM In the application, the M34E02 is soldered directly in the printed circuit module. The three Chip Enable inputs (E0, E1, E2) must be connected to V using a pull-up or pull-down resistor) through the DIMM socket (see ...
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... M34E02 5.1.2 DDR2 DIMM inserted in the application mother board As the final application cannot drive the E0 pin to V the write-protection with the PSWP instruction. Table 5 and Table 6 status. Table 5. Acknowledge when writing data or defining the write-protection (instructions with R/W bit=0) WC Status Input Level Permanently ...
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... Ack Address NoAck Not significant SWP NoAck Not significant CWP Ack Not significant PSWP Ack Not significant Ack Not significant M34E02 Ack Data byte Ack NoAck Not significant NoAck NoAck Not significant NoAck NoAck Not significant NoAck NoAck Not significant NoAck ...
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... M34E02 Figure 11. Serial presence detect block diagram DIMM Position 7 DIMM Position 6 DIMM Position 5 DIMM Position 4 DIMM Position 3 DIMM Position 2 DIMM Position 1 DIMM Position 0 AI01937 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices. 2. Common clock and common data are shared across all the devices. ...
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... Absolute maximum ratings Symbol T Storage Temperature STG V Input or Output range IO V Supply Voltage CC V Electrostatic Discharge Voltage (Human Body model) ESD 1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) 24/33 Parameter E0 Others (1) M34E02 Min. Max. Unit –65 150 °C –0.50 10.0 V –0.50 6.5 –0.5 6.5 V –4000 4000 V ...
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... M34E02 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... CC < 0. > 0.7V 500 CC 200 (1) Min Table SDA in Hi-Z CC, =100kHz c =100kHz 3. 1. –0.45 0.3 V 0. 1.7V CC M34E02 Unit (1) Max Unit ± 2 µA ± 2 µ µA 1 µ 0.4 V 0.2 V ...
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... M34E02 Table 12. AC characteristics Symbol Alt SCL t t CHCL HIGH t t CLCH LOW ( DL1DL2 DXCX SU:DAT t t CLDX HD:DAT t t CLQX DH ( CLQV AA ( CHDX SU:STA t t DLCL HD:STA t t CHDH SU:STO t t DHDL BUF ...
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... Figure 13. AC waveforms tCHCL SCL tDLCL SDA In tCHDX START Condition SCL SDA In tCHDH STOP Condition SCL tCLQV SDA Out 28/33 tCLCH tCLDX tDXCX SDA Change SDA Input tW Write Cycle tCLQX Data Valid M34E02 tCHDH tDHDL START STOP Condition Condition tCHDX START Condition AI00795C ...
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... M34E02 8 Package mechanical Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², package outline 1. Drawing is not to scale. 2. The central pad (the area the above illustration) is pulled, internally allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process ...
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... TSSOP8AM inches Typ. Min. 0.0020 0.0394 0.0315 0.0075 0.0035 0.1181 0.1142 0.0256 – 0.2520 0.2441 0.1732 0.1693 0.0236 0.0177 0.0394 0° 8 M34E02 Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 – 0.2598 0.1772 0.0295 8° ...
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... ST Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Part numbering M34E02 – ...
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... Vcc=3/6V, added to changed from 100kHz max, t CHCL CLCH DXCX CLQV Internal device inserted. I modified in Table 11: DC CC1 and Note 2 added to Figure 15 Summary removed from Table 7: Absolute LEAD M34E02 changed for EiH Table 11 CHDX DLCL reset. ...
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... M34E02 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...