m48z128 STMicroelectronics, m48z128 Datasheet - Page 7

• Manufacturer Part Number: m48z128
• Description: 5.0v Or 3.3v, 1 Mbit 128 Kbit X 8 Zeropower Sram
• Manufacturer: STMicroelectronics

OPERATING MODES
The M48Z128/Y/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single V
condition. When V
write protects the SRAM, providing a high degree
Table 3. Operating Modes
Note: X = V
READ Mode
The M48Z128/Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 1,048,576 locations in
the static storage array. Thus, the unique address
specified by the 17 address inputs defines which
one of the 131,072 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G (Output Enable) access times are also sat-
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
1. See
IH
A0-A16
E
G
DQ0-DQ7
Table 11., page 14
or V
IL
; V
CC
V
SO
CC
SO
= Battery Back-up Switchover Voltage.
supply for an out of tolerance
4.75 to 5.5V
is out of tolerance, the circuit
4.5 to 5.5V
3.0 to 3.6V
to V
V
V
PFD
or
or
for details.
SO
CC
(1)
(min)
AVQV
(1)
) after the last
tAVQV
tELQX
tELQV
tGLQX
tGLQV
V
V
V
V
E
X
X
IH
IL
IL
IL
tAVAV
VALID
V
V
G
X
X
X
X
IH
of data security in the midst of unpredictable sys-
tem operation brought on by low V
below the switchover voltage (V
cuitry connects the battery which maintains data
until valid power returns.
IL
isfied. If the E and G access times are not met, val-
id data will be available after the later of Chip
Enable Access time (t
cess Time (t
state Data I/O signals is controlled by E and G. If
the outputs are activated before t
lines will be driven to an indeterminate state until
t
and G remain low, output data will remain valid for
Output Data Hold time (t
minate until the next Address Access.
AVQV
. If the address inputs are changed while E
V
V
V
W
X
X
X
IH
IH
IL
M48Z128, M48Z128Y, M48Z128V*
DATA OUT
GLQV
tAXQX
DQ0-DQ7
High Z
High Z
High Z
High Z
). The state of the eight three-
D
D
OUT
tGHQZ
IN
ELQV
AXQX
) or Output Enable Ac-
Battery Back-up Mode
) but will go indeter-
CMOS Standby
SO
), the control cir-
CC
Standby
tEHQZ
AVQV
AI01197
Power
Active
Active
Active
. As V
, the data
CC
falls
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