m58lw064d STMicroelectronics, m58lw064d Datasheet - Page 17

• Manufacturer Part Number: m58lw064d
• Description: 64 Mbit 8mb X8, 4mb X16, Uniform Block 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

Table 4. Commands
Note: 1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program
Table 5. Configuration Codes
Note: 1. DQ2-DQ7 are reserved
Read Electronic Signature
Configuration
Configure STS command
Program/Erase Suspend
Program/Erase Resume
Read Status Register
Clear Status Register
Read Memory Array
Word/Byte Program
Protection Register
Write to Buffer and
Blocks Unprotect
2. For Identifier addresses and data refer to
3. For Query Address and Data refer to
Code
2. When STS pin is pulsing it remains Low for a typical time of 250ns.
00h
01h
02h
03h
Block Protect
Read Query
Block Erase
Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, PRA Protection register address,
PRD Protection Register Data, CC Configuration Code.
Command
Program
Program
DQ1
0
0
1
1
DQ2
0
1
0
1
4 + N Write
2
1
2
2
1
1
2
2
2
2
2
2
2
Ready/Busy
Pulse on Erase
complete
Pulse on
Program
complete
Pulse on Erase
or Program
complete
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Op. Addr. Data
Mode
1st Cycle
APPENDIX B., COMMON FLASH INTERFACE -
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 6., Read Electronic
FFh
E8h
B0h
D0h
C0h
B8h
90h
70h
98h
50h
20h
40h
10h
60h
60h
V
operations
Hi-Z when the
memory is ready
Pulse Low then
High when
operation
completed
OL
during P/E
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
Op.
STS Pin
(2)
2nd Cycle
IDA
QA
Addr.
PRA
RA
BA
PA
BA
BA
Signature.
X
X
X
(3)
(2)
Bus Operations
The STS pin is Low during Program and
Erase operations and high impedance when
the memory is ready for any Read, Program
or Erase operation.
Supplies a system interrupt pulse at the end
of a Block Erase operation.
Supplies a system interrupt pulse at the end
of a Program operation.
Supplies a system interrupt pulse at the end
of a Block Erase or Program operation.
IDD
QD
Data
SRD
PRD
D0h
01h
RD
PD
CC
D0
N
(3)
(2)
Write
Op. Addr. Data Op. Addr. Data
CFI.
Subsequent
PA
Description
PD Write
M58LW064D
Final
X
17/50
D0h