m58lw032c STMicroelectronics, m58lw032c Datasheet
m58lw032c
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... PROGRAM and ERASE SUSPEND I COMMON FLASH INTERFACE I 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE I – Manufacturer Code: 0020h – Device Code M58LW032C: 8822h I PACKAGES – Compliant with Lead-Free Soldering Processes – Lead-Free Versions August 2004 32 Mbit (2Mb x16, Uniform Block, Burst) 3V Supply Flash Memory Figure 1 ...
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... M58LW032C TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TSOP56 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. TBGA64 Connections (Top view through package Figure 5. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A1-A21 Data Inputs/Outputs (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W) ...
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... Figure 8. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 25 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program/Erase Controller Status Bit (SR7 Erase Suspend Status Bit (SR6 Erase Status Bit (SR5 Program Status Bit (SR4 Status Bit (SR3 PEN Program Suspend Status Bit (SR2 M58LW032C 3/61 ...
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... M58LW032C Block Protection Status Bit (SR1 Reserved (SR0 Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MAXIMUM RATING Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9. AC Measurement Input Output Waveform Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14. DC Characteristics Figure 11 ...
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... Figure 29.Protection Register Program Flowchart and Pseudo Code Figure 30.Command Interface and Program Erase Controller Flowchart ( Figure 31.Command Interface and Program Erase Controller Flowchart ( Figure 32.Command Interface and Program Erase Controller Flowchart (c REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 M58LW032C 5/61 ...
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... M58LW032C SUMMARY DESCRIPTION M58LW032C Mbit (2Mb x16) non-volatile memory that can be read, erased and repro- grammed. These operations can be performed us- ing a single low voltage (2.7V to 3.6V) core supply. On power-up the memory defaults to Read mode with an asynchronous bus where it can be read in the same way as a non-burst Flash memory. ...
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... RP V STS PEN DDQ SSQ NC AI06208 M58LW032C Address inputs Data Inputs/Outputs Chip Enable Output Enable Clock Latch Enable Valid Data Ready Status/(Ready/Busy) Reset/Power-Down Program/Erase Enable Write Enable Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground Not Connected Internally ...
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... M58LW032C Figure 3. TSOP56 Connections 8/ A21 A20 A19 A18 A17 A16 V DD A15 A14 A13 A12 M58LW032C V PEN A11 A10 STS DQ15 DQ7 DQ14 DQ6 V SS DQ13 DQ5 DQ12 DQ4 ...
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... A8 V PEN A13 A9 E A14 A7 A10 A12 A15 A5 A11 RP NC DQ9 DQ3 DQ4 DQ10 DQ11 DQ12 NC DQ2 V DDQ DQ5 DQ13 M58LW032C A18 NC NC A19 R NC A20 A21 NC A16 A17 NC DQ15 STS DQ6 DQ14 W V SSQ DQ7 NC ...
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... M58LW032C Figure 5. Block Addresses Total Mbit Blocks Note: Also see APPENDIX A., Table 25. 10/61 Word (x16) Bus Width 1FFFFFh 1 Mbit or 64 KWords 1F0000h 1EFFFFh 1 Mbit or 64 KWords 1E0000h 01FFFFh 1 Mbit or 64 KWords 010000h 00FFFFh 1 Mbit or 64 KWords 000000h for a full listing of the Block Addresses. ...
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... Synchronous Burst Read operations when the Burst Length is set to Continuous. The Valid Reset/Power- Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready Low, V M58LW032C , for at least t . When IL PLPH , the Status Regis- ...
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... M58LW032C dicates that the data is not, or will not be valid. Val- id Data Ready in a high-impedance state indicates that valid data is or will be available. Unless Synchronous Burst Read has been select- ed, Valid Data Ready is high-impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique System Ready signal ...
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... M58LW032C . The Address Inputs are IL 16 and 17, Write AC Wave- 18 and 19, Write AC Character- , and the outputs are high impedance, . The power consump- IH during a program or IH A1-A21 DQ0-DQ15 Address Data Output or Hi-Z IL Address Data Output ...
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... M58LW032C READ MODES Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchro- nous; if the data output is synchronized with clock, the read operation is synchronous. ...
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... Single Synchronous Read. Single nous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Single Syn- chronous Reads are used to read the Status Reg- ister, CFI, Electronic Signature and Block Protection Status. M58LW032C Synchro- 15/61 ...
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... M58LW032C CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. The Configuration Register bits are de- scribed in Table 3. They specify the selection of the burst length, burst type, burst X and Y laten- cies and the Read operation. See Figures for examples of Synchronous Burst Read configu- rations ...
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... X 1 Sequential 0 Falling Clock edge X 1 Rising Clock edge Reserved 001 4 Words XXX 010 8 Words 111 Continuous – AVQV LLKH QVKH SYSTEM MARGIN + < KHQV SYSTEM MARGIN QVKH K. M58LW032C Description < integer number from and t K. (1) K 17/61 ...
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... M58LW032C Table 4. Burst Type Definition Starting x4 x4 Addres Sequential Interleaved s 0 0-1-2-3 0-1-2-3 1 1-2-3-0 1-0-3-2 2 2-3-0-1 2-3-0-1 3 3-0-1-2 3-2-1-0 4 – – 5 – – 6 – – 7 – – 8 – – Figure 6. Burst Configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 18/ Sequential Interleaved 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 – – VALID VALID ...
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... Figure 7. Burst Configuration X-2-2 ADD VALID L DQ 5-2-2-2 DQ 6-2-2-2 DQ 7-2-2-2 DQ 8-2-2 VALID NV NV=NOT VALID M58LW032C VALID NV VALID NV VALID NV VALID NV NV VALID VALID NV VALID NV AI05513 19/61 ...
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... M58LW032C COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. The Commands are summarized in 5., Commands. Refer to Table 5. with the text descriptions below. After power- Reset operation the memory enters Read mode ...
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... Status Register. Set Configuration Register Command. The Set Configuration Register command is used to write a new value to the Burst Configuration Con- trol Register which defines the burst length, type, M58LW032C Table 9. C., Figure 24., Program Suspend Code, and Code, for suggested flowcharts on using ...
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... M58LW032C X and Y latencies, Synchronous/Asynchronous Read mode and the valid Clock edge configura- tion. Two Bus Write cycles are required to issue the Set Configuration Register command. Once the com- mand is issued the memory returns to Read mode Read Memory Array command had been is- sued ...
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... Table 7., Read Electronic Signature. APPENDIX B., COMMON FLASH INTERFACE - Mode STS Pin V during P/E OL operations Hi-Z when the memory is ready Pulse Low then High when operation (2) completed M58LW032C Subsequent Final Data Op. Addr. Data Op. Addr. Data RD (3) IDD SRD ( Write PA PD Write ...
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... M58LW032C Table 7. Read Electronic Signature Code Manufacturer Code Device Code Block Protection Status Configuration Register Protection Register Note: 1. SBA is the Start Base Address of each block, BCR is Configuration Register data, PRD is Protection Register Data. 2. Base Address, refer to Figure 8. Table 8. Read Protection Register ...
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... Maximum value measured at worst case conditions for both temperature and V 5. Maximum value measured at worst case conditions for both temperature and V M58LW032C (1,2) Min Typ 1 (3) 192 0.75 100,000 20 after 100,000 program/erase cycles M58LW032C Unit (2) Max (4) s 4.8 ( (4) s 110 (4) µs 576 (4) µs 48 (5) µs 20 (5) µ ...
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... M58LW032C STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Reg- ister command can be issued ...
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... Low by a Clear Status Register com- Status PEN mand or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (SR0). SR0 of the Status Register is reserved. Its value should be masked. M58LW032C Pro Block , ...
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... M58LW032C Table 10. Status Register Bits OPERATION Program/Erase Controller active Write Buffer not ready Write Buffer ready Write Buffer ready in Erase Suspend Program suspended Program suspended in Erase Suspend Program/Block Protect completed successfully Program completed successfully in Erase Suspend Program/Block protect failure due to incorrect command sequence ...
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... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. Ta- not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. STMicroelectronics SURE Program and other rel- evant quality documents. Parameter M58LW032C Refer also to Value Unit Min Max –40 125 ° ...
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... Grade 1 Grade 6 Figure 10. AC Measurement Load Circuit V DDQ 0.5 V DDQ AI00610 0.1µF Test Condition OUT Conditions summarized M58LW032C 90, 110 Min Max 2.7 3.6 1 – DDQ 0.5 V DDQ 1 ...
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... Program or Erase operation in progress 100µ –100µA OH tAVAV VALID tELQV tELQX tGLQV tGLQX tAVQV OUTPUT M58LW032C Min Max ±1 DDQ ±5 DDQ = 6MHz 20 = 50MHz –0 0.3 DDQ ...
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... Parameter Min M58LW032C Unit 90 110 90 110 90 110 110 tEHLX tEHQZ tEHQX tGHQZ tGHQX OUTPUT AI06256b M58LW032C Unit 90 110 ...
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... Note: For other timings see Table 15., Asynchronous Bus Read AC Characteristics. Figure 13. Asynchronous Page Read AC Waveforms A1-A2 A3-A21 DQ0-DQ15 Note: Asynchronous Read CR15 = 1 Parameter VALID VALID tAVQV tELQV tELQX tGLQV tGLQX OUTPUT M58LW032C M58LW032C 90 110 Min 10 10 Min 10 10 Min 10 10 Min 0 0 Min 10 10 Min 0 ...
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... Note: For other timings see Table 15., Asynchronous Bus Read AC Characteristics. Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled A1-A21 E L tELWL G tGHWL W DQ0-DQ15 RB V PEN 34/61 Parameter Min Max VALID tAVWH tWHAX tWHEH tWLWH tWHWL tDVWH INPUT tWHDX tVPHWH tWHBL M58LW032C Unit 90, 110 tWHGL AI06258 ...
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... Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled A1-A21 L tELLL E tELWL G tGHWL W DQ0-DQ15 RB V PEN VALID tAVLH tLHAX tLLLH tWLLH tLHWH tWHEH tWLWH tWHWL tDVWH INPUT tWHDX tVPHWH tWHBL M58LW032C tLHGL tWHGL AI06259 35/61 ...
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... Write Enable Low to Latch Enable High WLLH 36/61 Parameter Min Min Min Min Min Min Min Min Min Min Min Min Max Min Min Min Min Min Min Min M58LW032C Unit 90, 110 ...
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... Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled A1-A21 L tWLLL W tWLEL G tGHEL E DQ0-DQ15 RB V PEN VALID tAVEH tEHAX tEHWH tELEH tEHEL tDVEH INPUT tEHDX tVPHEH tEHBL VALID tAVLH tLHAX tAVEH tEHAX tLLLH tLHEH tELLH tEHWH tELEH tEHEL tDVEH INPUT tEHDX tVPHEH tEHBL M58LW032C tEHGL tLHGL tEHGL AI06260 AI06261 37/61 ...
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... Write Enable Low to Latch Enable Low WLLL 38/61 Parameter Min Min Min Min Max Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min M58LW032C Unit 90, 110 500 ...
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K tKHLL tKHAX VALID A1-A21 tLLKH tLHAX tLLLH L tAVKH tAVLH tELKH tELLH E G DQ0-DQ15 X-1 X X+Y tGLKH tKHQV tKHQX tQVKH Q1 Q2 X+2Y X+2Y+1 X+2Y+2 tEHQZ tEHQX tGHQZ tGHQX Q3 AI06262 ...
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... Valid Data Ready Low to Valid Clock Edge RLKH Note: For other timings see Table 15., Asynchronous Bus Read AC Characteristics. 40/ tRLKH (3) Depending on the Valid Data Ready pin capacitance load an Parameter V AI05510 M58LW032C Unit 90, 110 Min 7 ns Min 10 ns Min 10 ns Min 10 ns ...
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... Reset/Power-Down Low to Reset/Power-Down High PLPH t Reset/Power-Down Low to Ready High PLRH t Supply Voltages High to Reset/Power-Down High VDHPH Power-Up and Reset Parameter M58LW032C tPLRH tPLPH Reset during Program or Erase M58LW032C 90 110 Max 130 150 Min 100 100 Max 30 30 Min 0 0 AI05521 Unit ...
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... M58LW032C PACKAGE MECHANICAL Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline mm, Package Outline 1 N/2 TSOP-b Note: Drawing is not to scale. Table 22. TSOP56 - 56 lead Plastic Thin Small Outline mm, Package Mechanical Data Symbol Typ A A1 0.100 A2 1.000 B 0.220 20.000 D1 18.400 e 0.500 E 14 ...
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... M58LW032C ddd A2 BGA-Z23 inches Typ Min 0.0118 0.0079 0.0315 0.0138 0.3937 0.3898 0.2756 – 0.0394 – 0.5118 0.5079 0.2756 – ...
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... F = Lead-free and RoHS Package, Tape & Reel Packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 44/61 M58LW032C DD 110 ...
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... Table 25. Block Addresses Block Address Range Number (x16 Bus Width) 32 1F0000h-1FFFFFh 31 1E0000h-1EFFFFh 30 1D0000h-1DFFFFh 29 1C0000h-1CFFFFh 28 1B0000h-1BFFFFh 27 1A0000h-1AFFFFh 26 190000h-19FFFFh 25 180000h-18FFFFh 24 170000h-17FFFFh 23 160000h-16FFFFh 22 150000h-15FFFFh 21 140000h-14FFFFh 20 130000h-13FFFFh 19 120000h-12FFFFh 18 110000h-11FFFFh 17 100000h-10FFFFh 16 0F0000h-0FFFFFh 15 0E0000h-0EFFFFh 14 0D0000h-0DFFFFh 13 0C0000h-0CFFFFh 12 0B0000h-0BFFFFh 11 0A0000h-0AFFFFh 10 090000h-09FFFFh 9 080000h-08FFFFh 8 070000h-07FFFFh 7 060000h-06FFFFh 6 050000h-05FFFFh 5 040000h-04FFFFh 4 030000h-03FFFFh 3 020000h-02FFFFh 2 010000h-01FFFFh 1 000000h-00FFFFh M58LW032C 45/61 ...
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... M58LW032C APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
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... Organization Sync./Async. 05h Maximum number of bytes in Write Buffer, 2 00h 01h Bit7-0 = number of Erase Block Regions in device 1Fh Number (n-1) of Erase Blocks of identical size; n=64 00h 00h Erase Block Region Information x 256 bytes per Erase block (128K bytes) 02h M58LW032C Description Description n 47/61 ...
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... M58LW032C Table 30. Block Status Register Address A21-A1 (1) (BA+2)h Note specifies the block address location, A21-A17. 2. Not Supported. Table 31. Extended Query information Address Address offset A21-A2 (P)h 31h 50h (P+1)h 32h 52h (P+2)h 33h 49h (P+3)h 34h (P+4)h 35h (P+5)h 36h (P+6)h 37h (P+7)h 38h (P+8)h 39h (P+9)h 3Ah (P+A)h 3Bh (P+B)h 3Ch (P+C)h 3Dh ...
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... Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV. Data (Hex) x16 Bus Width 03h Synchronous mode configuration fields n+1 01h n where 2 n+1 02h n where 2 07h Burst Continuous M58LW032C Description is the number of Words for the burst Length = 4 is the number of Words for the burst Length = 8 49/61 ...
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... M58LW032C APPENDIX C. FLOW CHARTS Figure 23. Write to Buffer and Program Flowchart and Pseudo Code Note 1: N+1 is number of Words to be programmed Note 2: Next Program Address must have same A5-A21. Note 3: A full Status Register Check must be done to check the program operation's success. 50/61 Start ...
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... Read data from another block Write D0h Program Continues NO NO Program Complete Write FFh Read Data M58LW032C Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while SR7 = 1 If SR2 = 0, Program completed Read Memory Array command: – write FFh – ...
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... M58LW032C Figure 25. Erase Flowchart and Pseudo Code Start Write 20h Write D0h to Block Address Read Status Register SR7 = 1 YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES SR1 = 0 YES End Note error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper- ations ...
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... Program Write D0h Erase Continues NO NO Erase Complete Write FFh Read Data M58LW032C Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while SR7 = 1 If SR6 = 0, Erase completed Read Memory Array command: – write FFh – ...
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... M58LW032C Figure 27. Block Protect Flowchart and Pseudo Code Start Write 60h Block Address Write 01h Block Address Read Status Register SR7 = 1 YES SR3 = 1 NO SR4, SR5 = 1,1 NO SR4 = 1 NO Write FFh Block Protect Sucessful 54/61 NO YES V PEN Invalid Error YES Invalid Command Sequence Error ...
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... YES V PEN Invalid Error YES Invalid Command Sequence Error YES Blocks Unprotect Error M58LW032C Blocks Unprotect Command – write 60h, Block Adress – write D0h, Block Adress do: – read status register while SR7 = 1 If SR3 = 1, V PEN Invalid Error If SR4 = 1, SR5 = 1 Invalid Command ...
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... M58LW032C Figure 29. Protection Register Program Flowchart and Pseudo Code Start Write C0h Write PR Address, PR Data Read Status Register SR7 = 1 YES SR3, SR4 = 1,1 NO SR1, SR4 = 0,1 NO SR1, SR4 = 1,1 NO Write FFh PR Program Sucessful Note Protection Register 56/61 NO YES V PEN Invalid Error YES Protection Register Program Error ...
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... Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend 70h YES READ NO 50h STATUS YES CLEAR E8h STATUS PROGRAM BUFFER LOAD NO D0h PROGRAM COMMAND ERROR M58LW032C NO YES NO (1) 20h YES ERASE FFh SET-UP YES NO YES D0h YES C ERASE A COMMAND ERROR READ ...
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... M58LW032C Figure 31. Command Interface and Program Erase Controller Flowchart (b) WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY PROGRAM BUFFER LOAD NO PROGRAM D0h COMMAND ERROR YES c 58/61 B READ STATUS READ ARRAY YES NO FFh NO YES ERASE SUSPENDED YES YES 70h NO YES ...
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... YES NO FFh NO YES PROGRAM SUSPENDED YES YES 70h NO YES 90h NO YES 98h NO NO YES READ D0h STATUS M58LW032C C PROGRAM (READ STATUS) Program/Erase Controller READY Status bit in the Status ? Register NO NO B0h YES READ STATUS PROGRAM SUSPEND READY ? NO READ STATUS (PROGRAM RESUME) ...
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... M58LW032C REVISION HISTORY Table 32. Document Revision History Date Version 11-Mar-2002 -01 First Issue (Data Brief) 10-Jul-2002 -02 Document expanded to full Product Preview Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 02 equals 2 ...
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