psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 30

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

Register bit definition
30/120
VM register
On reset, bit1-bit4 are loaded to configurations that are selected by the user in PSDsoft.Bit0
and bit7 are always cleared on reset.Bit0-bit4 are active only when the device is configured
for the 8031 and compatible MCU families.
Memory_ID0 register
Bit 7
S_size 3
Peripheral mode 0 = Peripheral mode of port F is disabled.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
Peripheral
mode
Bit 7
S_size[3:0] 0h = There is no SRAM
F_size[3:0] 4h = Primary Flash memory size is 4 Mbit
Boot_code 0 = PSEN cannot access secondary NVM.
PLD Array
Boot_data 0 = RD cannot access secondary NVM.
SR_code 0 = PSEN cannot access SRAM.
FL_code 0 = PSEN cannot access primary Flash memory.
FL_data 0 = RD cannot access primary Flash memory.
CNTL0
Bit 6
S_size 2
(set to ’0’)
not used
Bit 6
5h = Primary Flash memory size is 8Mbit
1h = SRAM size is 16 Kbit
3h = SRAM size is 64 Kbit
0 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
1 = ALE input to the PLD AND array is disconnected, saving power.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
1 = PSEN can access SRAM.
1 = PSEN can access secondary NVM.
1 = PSEN can access primary Flash memory.
1 = RD can access secondary NVM.
1 = RD can access primary Flash memory.
1 = Peripheral mode of port F is enabled.
Bit 5
S_size 1
(set to ’0’)
not used
Bit 5
Bit 4
S_size 0
FL_data
Bit 4
Bit 3
F_size 3
Boot_data
Bit 3
Bit 2
F_size 2
FL_code
Bit 2
Bit 1
F_size 1
Boot_code
Bit 1
PSD835G2
Bit 0
F_size 0
SR_code
Bit 0