lh28f400su-lc Sharp Microelectronics of the Americas, lh28f400su-lc Datasheet - Page 16
lh28f400su-lc
Manufacturer Part Number
lh28f400su-lc
Description
512k 256k Flash Memory
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LH28F400SU-LC.pdf
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LH28F400SU-LC
16
Figure 12. Two-Byte Serial Writes with Compatible Status Registers (56-pin TSOP, 44-pin SOP)
OPERATION COMPLETE
READ COMPATIBLE
READ COMPATIBLE
STATUS REGISTER
STATUS REGISTER
WRITE DATA/A
DATA/ADDRESS
WRITE FBH
CSR.4, 5 =
ANOTHER
CSR.7 =
CSR.7 =
START
2-BYTE
WRITE
WRITE
1
1
0
NO
-1
0
1
0
YES
(NOTE)
OPERATION
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Cycle notes for description of codes.
Read
Write
Write
Write
Read
BUS
COMMAND
2-Byte
Write
4M (512K × 8, 256K × 16) Flash Memory
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
D = FBH
A = X
D = WD
A
of Data Register.
A
of Data Register.
Other Addresses = X
D = WD
A = WA
Internally, A
complemented to load the
alternate byte location of the
Data Register.
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
-1
-1
= 0 loads low byte
= 1 loads high byte
COMMENTS
-1
is automatically
28F400SUH-LC15-10
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