lh28f400su-lc Sharp Microelectronics of the Americas, lh28f400su-lc Datasheet - Page 6

• Manufacturer Part Number: lh28f400su-lc
• Description: 512k 256k Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F400SU-LC
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP
Unlocked Blocks can be used. If used, Erase is per-
formed with reflecting actual lock status, and after that
Write and Block Erase can be used.
Register (CSR) which is 100% compatible with the
LH28F008SA Flash memory’s Status Register. This reg-
ister, when used alone, provides a straightforward
upgrade capability to the LH28F400SU-LC from a
LH28F008SA-based design.
RY
tie many RY
figuration such as a Resident Flash Array.
access time of 150 ns (t
3.6 V) over the commercial temperature range. A corre-
sponding maximum access time of 190 ns (t
2.7 V (0 to +70°C) is achieved for reduced power con-
sumption applications.
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
when the RP
transitions low. This mode brings the device power con-
sumption to less than 8 µA, and provides additional write
protection by acting as a device reset pin during power
transitions. A reset time of 750 ns is required from RP
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR register is cleared.
CE
control pins as CMOS levels. In this mode, the device
draws an I
6
When the device power-up or RP
The LH28F400SU-LC contains a Compatible Status
The LH28F400SU-LC incorporates an open drain
The LH28F400SU-LC is specified for a maximum
The LH28F400SU-LC incorporates an Automatic
In APS mode, the typical I
A Deep Power-Down mode of operation is invoked
A CMOS Standby mode of operation is enabled when
»
»
/ BY
transitions high and RP
»
output pin. This feature allows the user to OR-
CC
»
/ BY
»
standby current of 15 µA.
(called PWD on the LH28F008SA) pin
»
pins together in a multiple memory con-
ACC
) at 3.3 V operation (3.0 to
CC
»
»
stays high with all input
turns High, Erase All
current is 1 mA at 3.3 V.
»
turns High, Write
ACC
) at
»
MEMORY MAP
7FFFFH
7BFFFH
6FFFFH
6BFFFH
5FFFFH
5BFFFH
4FFFFH
4BFFFH
3FFFFH
3BFFFH
2FFFFH
2BFFFH
1FFFFH
1BFFFH
0FFFFH
0BFFFH
7C000H
77FFFH
73FFFH
6C000H
67FFFH
63FFFH
5C000H
57FFFH
53FFFH
4C000H
47FFFH
43FFFH
3C000H
37FFFH
33FFFH
2C000H
27FFFH
23FFFH
1C000H
17FFFH
13FFFH
0C000H
07FFFH
03FFFH
78000H
74000H
70000H
68000H
64000H
60000H
58000H
54000H
50000H
48000H
44000H
40000H
38000H
34000H
30000H
28000H
24000H
20000H
18000H
14000H
10000H
08000H
04000H
00000H
4M (512K × 8, 256K × 16) Flash Memory
Figure 5. Memory Map
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
28F400SUH-LC15-3
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