m29dw256g Numonyx, m29dw256g Datasheet - Page 35

• Manufacturer Part Number: m29dw256g
• Description: 256-mbit X16, Multiple Bank, Page, Dual Boot 3 V Supply Flash Memory
• Manufacturer: Numonyx

Write to Buffer Program command
Five successive steps are required to issue the Write to Buffer Program command:
1.
2.
3.
4.
5.
All the addresses used in the write to buffer program operation must lie within the same
page.
To program the content of the write buffer, this command must be followed by a Write to
Buffer Program Confirm command.
If an address is written several times during a write to buffer program operation, the
address/data counter will be decremented at each data load operation and the data will be
programmed to the last word loaded into the buffer.
Invalid address combinations or failing to follow the correct sequence of bus write cycles will
abort the write to buffer program.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a write to buffer program operation.
It is possible to detect program operation fails when changing programmed data from '0' to
'1', that is when reprogramming data in a portion of memory already programmed. The
resulting data will be the logical OR between the previous value and the current value.
After the write to buffer program operation has completed, the memory will return to read
mode, unless an error has occurred. When an error occurring bus read operations to the
bank being programmed will continue to output the status register (a bus reading operations
from banks different from those including the blocks being programmed output the memory
array content).
The Write to Buffer Program command starts with two unlock cycles
The third bus write cycle sets up the Write to Buffer Program command. The setup
code can be addressed to any location within the targeted block.
The fourth bus write cycle sets up the number of words/bytes to be programmed. Value
N is written to the same block address, where N+1 is the number of words/bytes to be
programmed. N+1 must not exceed the size of the write buffer or the operation will
abort.
The fifth cycle loads the first address and data to be programmed.
Use N bus write cycles to load the address and data for each word/byte into the write
buffer. Addresses must lie within the range from the start address+1 to the start
address +N-1. Optimum performance is obtained when the start address corresponds
to a 32-word/ 64-byte boundary. If the start address is not aligned to a 32-word/64-byte
boundary, the total programming time is doubled.
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