m29dw256g Numonyx, m29dw256g Datasheet - Page 45

• Manufacturer Part Number: m29dw256g
• Description: 256-mbit X16, Multiple Bank, Page, Dual Boot 3 V Supply Flash Memory
• Manufacturer: Numonyx

Table 14.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to read mode.
Exit Protection Command
Set
Enter Extended Block
Exit Extended Block
(10)
Enter Lock Register
Command Set
Lock Register Program
Lock Register Read
Enter Volatile Protection
Command Set
VPB Program
Read VPB Status
VPB Clear
Enter Non-volatile
Protection Command
Set
NVPB Program
Clear all NVPBs
Read NVPB Status
Enter NVPB Lock Bit
Command Set
NVPB Lock Bit Program
Read NVPB Lock Bit
Status
Enter Password Protection
Command Set
Password Program
Password Read
Password Unlock
Ad address, Dat data, BAd any address in the block, RD read data, PWDn password word 0 to 3, PWAn password address (n = 0 to 3), X don’t care. All values in the
table are in hexadecimal.
Grey cells represent read cycles. The other cells are write cycles.
DQ15 to DQ8 are ‘don’t care’ during unlock and command cycles. A23 to A16 are ‘don’t care’ during unlock and command cycles unless an address is required.
An Enter command sequence must be issued prior to any operation; it disables read and write operations from and to block 0. Read and write operations from any
other block are allowed.
DATA = lock register content.
Protected and unprotected states correspond to 00 and 01, respectively.
The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared non-volatile modify protection bits.
Only one portion of password can be programmed or read by each Password Program command.
The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
(4)
Command
Block protection commands
(4)
(4)
(6)
(7)
(7)
(4)
(8)(9)
2
2
3
2
1
3
2
1
3
2
2
1
3
1
3
2
4
7
2
3
4
(BKA)
(BKA)
BAd
BAd
BKA
555
555
555
555
555
555
555
Ad
00
00
X
X
X
X
X
X
X
X
X
1st
DATA
PWD0
RD(0)
RD(0)
RD(0)
Data
AA
A0
AA
A0
A0
AA
A0
AA
A0
AA
A0
AA
AA
80
25
90
(5)
(BKA)
(BKA)
(BKA)
PWAn
2AA
2AA
BAd
BAd
2AA
BAd
2AA
2AA
2AA
2AA
Ad
00
01
00
X
X
X
(1)(2)(3)
2nd
PWDn
PWD1
DATA
Data
55
(5)
55
00
01
55
00
30
55
00
55
03
00
55
55
(BKA)
(BKA)
BAd
555
555
555
555
555
555
Ad
02
00
3rd
PWD2
PWD0
Data
Bus operations
E0
C0
40
50
60
88
90
Ad
03
01
X
4th
PWD3
PWD1
Data
00
Ad
02
5th
PWD2
Data
Ad
03
6th
PWD3
Data
Ad
00
7th
45/84
Data
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