xc1765d Xilinx Corp., xc1765d Datasheet - Page 4
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xc1765d
Manufacturer Part Number
xc1765d
Description
Qpro Family Of Xc1700d Qml Configuration Proms
Manufacturer
Xilinx Corp.
Datasheet
1.XC1765D.pdf
(10 pages)
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QPRO Family of XC1700D QML Configuration PROMs
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs.
4
Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK
RESET
* For mode pin connections,
refer to the appropriate FPGA data sheet.
(Output)
(Output)
DOUT
CCLK
DIN
MODES*
RESET
(Low Resets the Address Pointer)
FPGA
Vcc
DOUT
DONE
CCLK
INIT
DIN
cycle before the FPGA I/Os become active.
3.3V
www.xilinx.com
1-800-255-7778
4.7K
CLK
CE
OE/RESET
DATA
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
V CC
V CC
PROM
V PP
V PP
CEO
CLK
CE
OE/RESET
DATA
DS070 (v2.1) June 1, 2000
Product Specification
Cascaded
Memory
Serial
DS027_02_052200
R