s-8211caj-m5t1g Seiko Instruments Inc., s-8211caj-m5t1g Datasheet - Page 20

• Manufacturer Part Number: s-8211caj-m5t1g
• Description: Battery Protection Ic For 1-cell Pack
• Manufacturer: Seiko Instruments Inc.

20
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211C Series
3. Overdischarge Status
4. Discharge Overcurrent Status (Discharge Overcurrent, Load Short-circuiting)
When the battery voltage falls below overdischarge detection voltage (V
and the detection continues for the overdischarge detection delay time (t
discharging control FET off to stop discharging. This condition is called the overdischarge status. Under the
overdischarge status, the VM pin voltage is pulled up by the resistor between the VM pin and VDD pin in the IC
(R
consumption is reduced to the power-down current consumption (I
status.
The resistance (R
overdischarge status.
The power-down status is released when a charger is connected and the voltage difference between the VM pin and
VDD pin becomes 1.3 V (typ.) or higher.
When a battery in the overdischarge status is connected to a charger and provided that the VM pin voltage is lower
than -0.7 V (Typ.), the S-8211C Series releases the overdischarge status and turns the discharging FET on when the
battery voltage reaches overdischarge detection voltage (V
When a battery in the overdischarge status is connected to a charger and provided that the VM pin voltage is not
lower than -0.7 V (Typ.), the S-8211C Series releases the overdischarge status when the battery voltage reaches
overdischarge release voltage (V
When a battery in the normal status is in the status where the voltage of the VM pin is equal to or higher than the
discharge overcurrent detection voltage because the discharge current is higher than the specified value and the
status lasts for the discharge overcurrent detection delay time, the discharge control FET is turned off and
discharging is stopped. This status is called the discharge overcurrent status.
In the discharge overcurrent status, the VM pin and VSS pin are shorted by the resistor between VM pin and VSS pin
(R
connected. When the load is disconnected, the VM pin returns to the V
This IC detects the status when the impedance between the EB+ pin and EB− pin (Refer to the Figure 14) increases
and is equal to the impedance that enables automatic restoration and the voltage at the VM pin returns to discharge
overcurrent detection voltage (V
Even if the connected impedance is smaller than automatic restoration level, the S-8211C Series will be restored to
the normal status from discharge overcurrent detection status when the voltage at the VM pin becomes the discharge
overcurrent detection voltage (V
The resistance (R
status.
VMD
VMS
). When voltage difference between the VM pin and VDD pin then is 1.3 V (Typ.) or lower, the current
) in the IC. However, the voltage of the VM pin is at the V
VMD
VMS
) between the VM pin and VDD pin is not connected in the discharge overcurrent detection
) between the VM pin and VSS pin is not connected in the power-down status and the
DIOV
DIOV
DU
) or higher.
) or lower, the discharge overcurrent status is restored to the normal status.
) or lower by connecting the charger.
Seiko Instruments Inc.
DL
) or higher.
DD
PDN
potential due to the load as long as the load is
SS
). This condition is called the power-down
DL
DL
potential.
) or longer, the S-8211C Series turns the
) during discharging in the normal status
Rev.5.0
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