ncp5306dw ON Semiconductor, ncp5306dw Datasheet - Page 20

• Manufacturer Part Number: ncp5306dw
• Description: Threephase Vrm 9.0 Buck Controller
• Manufacturer: ON Semiconductor

where:
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
where:
copper clad circuit boards will have approximate thermal
resistances (θ
Vf
t_nonoverlap is the non−overlap time between the upper
When the MOSFET power dissipations are known, the
θ
θ
θ
T
T
For TO−220 and TO−263 packages, standard FR−4
T
JC
SA
A
J
diode at the converter output current.
MOSFET;
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used);
temperature;
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
control IC.
diode
is the total thermal impedance (θ
is the worst case ambient operating temperature.
is the junction−to−case thermal impedance of the
is the specified maximum allowed junction
is the sink−to−ambient thermal impedance of the
is the forward voltage of the MOSFET’s intrinsic
SA
) as shown below:
(in
Pad Size
0.50/323
0.75/484
1.00/645
1.50/968
2
q T t (T J * T A ) P D
/mm
2
)
L1
0 A
Lx
0 A
Single−Sided
1 oz. Copper
R
R
60−65°C/W
55−60°C/W
50−55°C/W
45−50°C/W
CS1
CSx
C
C
CS1
CSx
JC
+ θ
Figure 24. AVP Circuitry at No−Load
CS1
CSx
CS
SA
REF
);
+
−
+
−
G
G
http://onsemi.com
VDRP
VDRP
(28)
Σ
V
20
V
CORE
DRP
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading and component
variations (i.e., worst case MOSFET R
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, it is advisable to have as
much heatsink area as possible. All too often, new designs are
found to be too hot and require re−design to add heatsinking.
6. Adaptive Voltage Positioning
Voltage Positioning: R
no−load “high” voltage position and R
full−load “droop” voltage.
pin of the controller. At no load, this resistor will conduct the
internal bias current of the V
drop from V
regulates V
V
condition is shown in Figure 24.
voltage decrease below the VID setting (ΔV
determine the V
decrease is specified in the design guide for the processor
that is available from the manufacturer. The V
is determined by the value of the resistor from R
ground (see Figure 4 in the data sheet for a graph of
IBIAS
calculated:
I
CORE
= VID
DRP
= VID + IBIAS
COMP
As with any power design, proper laboratory testing
There are two resistors that determine the Adaptive
Resistor R
To calculate R
R
= 0
VFB
DRP
, will be lower by the amount IBIAS
Error
Amp
R FB + DV NO−LOAD IBIAS VFB
V
versus R
+
−
FB
FB
FB
FB
VFB
to the V
= VID
FB
to the DAC setting, the output voltage,
is connected between V
FB
I
FB
VID Setting
bias current. Usually, the no−load voltage
w R
, the designer must specify the no−load
IBIAS
OSC
= IBIAS
R
FB
+ −
CORE
FB
FB
). The value of R
VFB
and R
VFB
V
pin. Because the error amplifier
CORE
FB
pin and develop a voltage
DRP
. R
DRP
FB
CORE
DS(on)
FB
VFB
establishes the
determines the
NO−LOAD
FB
and the V
can then be
). Also, the
bias current
⋅ R
FB
OSC
. This
) and
(29)
FB
to