ncp5306dw ON Semiconductor, ncp5306dw Datasheet - Page 21

• Manufacturer Part Number: ncp5306dw
• Description: Threephase Vrm 9.0 Buck Controller
• Manufacturer: ON Semiconductor

Constant of the Current Sense Network Is Too Short
Constant of the Current Sense Network Is Too Long
Figure 26. V
Figure 27. V
(Slow): V
(Fast): V
DRP
DRP
DRP
DRP
and V
Tuning Waveforms. The RC Time
Tuning Waveforms. The RC Time
and V
OUT
OUT
L1
I
Lx
I
MAX
MAX
Respond Too Slowly.
R
R
/3
/3
Both Overshoot.
CS1
CSx
V
CORE
C
C
CS1
CSx
= VID − I
= VID − (I
Figure 25. AVP Circuitry at Full−Load
CS1
CSx
CS
REF
MAX
DRP
+
−
+
−
G
G
http://onsemi.com
VDRP
VDRP
w R
− IBIAS
L
w G
Σ
V
I
VDRP
VFB
MAX
21
DRP
) w R
I
I
• R
DRP
FBK
V
be at the DAC voltage. This resistor will conduct zero
current. However, at full−load, the voltage at the V
will increase proportional to the output inductor’s current
while V
will be conducted from V
will be large enough to supply the V
a voltage drop from V
converter’s output voltage will be reduced. This condition is
shown in Figure 25.
the full−load voltage reduction from the VID (DAC) setting
(ΔV
V
reduction is specified in the design guide for the processor
that is available from the manufacturer. To predict the
voltage increase at the V
designer must consider the output inductor’s resistance
(R
points (R
sense to the V
R DRP +
from the VID (DAC) setting. Δ
voltage change from the no−load AVP setting.
7. Current Sensing
network (R
= VID +
w R
FB
DRP
COMP
Resistor R
To determine the value of R
The value of R
ΔV
For inductive current sensing, choose the current sense
L
L
FB
I
= I
FB
DRP
= I
), the PCB trace resistance between the current sense
• G
OUT,FULL−LOAD
pins. At no−load, the V
/R
R
OUT,FULL−LOAD
DRP
MAX
DV DRP + I O,MAX @ (R L ) R PCB ) @ G VDRP
DRP
VDRP
pin at full−load. Usually, the full−load voltage
DRP
Error
FB
Amp
PCB
− IBIAS
(IBIAS VFB ) DV OUT,FULL−LOAD R FB )
• R
will still be regulated to the DAC voltage. Current
V
CSx
+ IBIAS
R CSx @ C CSx + Lo (R L ) R PCB )
+
−
FB
DRP
L
) and the controller IC’s gain from the current
DRP
• G
, C
= VID
VFB
DRP
VDRP
is connected between the V
CSx
VID Setting
VFB
pin (G
IBIAS
) and predict the voltage increase at the
, x = 1, 2 or 3) to satisfy
R
+ −
can then be calculated:
/R
w R
I
is the full−load voltage reduction
FB
FB
DRP
VFB
DRP
VDRP
FB
DRP
FB
DV DRP
V
DRP
DRP
CORE
to V
pin at full−load (ΔV
to V
):
VOUT,FULL−LOAD
and the V
, the designer must specify
FB
CORE
FB
by R
bias current and cause
across R
DRP
FB
pins will both
. This current
DRP
is not the
DRP
FB
DRP
and the
. The
), the
(30)
(31)
(32)
pin