lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 17

• Manufacturer Part Number: lm5066pmhx
• Description: High Voltage System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

the FB pin is below its threshold, the 20 µA current source at
FB is disabled. As the output voltage increases, taking FB
above its threshold, the current source is enabled, sourcing
current out of the pin, raising the voltage at FB to provide
threshold hysteresis. The PGD output is forced low when ei-
ther the UVLO/EN pin is below its threshold or the OVLO pin
is above its threshold. The status of the PGD pin can be read
via the PMBus interface in either the STATUS_WORD (79h)
or DIAGNOSTIC_WORD (E1h) registers.
VDD Sub-Regulator
The LM5066 contains an internal linear sub-regulator which
steps down the input voltage to generate a 4.9V rail used for
powering low voltage circuitry. The VDD sub-regulator should
be used as the pull-up supply for the CL, RETRY, ADR2,
ADR1, ADR0 pins if they are to be tied high. It may also be
used as the pull-up supply for the PGD and the SMBus signals
(SDA, SCL, SMBA). The VDD sub-regulator is not designed
to drive high currents and should not be loaded with other
integrated circuits. The VDD pin is current limited to 30mA in
order to protect the LM5066 in the event of a short. The sub-
regulator requires a ceramic bypass capacitance having a
value of 1 µF or greater to be placed as close to the VDD pin
as the PCB layout allows.
Remote Temperature Sensing
The LM5066 is designed to measure temperature remotely
using an MMBT3904 NPN transistor. The base and collector
of the MMBT3904 should be connected to the DIODE pin and
the emitter to the LM5066 ground. Place the MMBT3904 near
the device that requires temperature sensing. If the temper-
ature of the hot swap pass MOSFET, Q
the MMBT3904 should be placed as close to Q
allows. The temperature is measured by means of a change
in the diode voltage in response to a step in current supplied
by the DIODE pin. The DIODE pin sources a constant 9.4 µA
but pulses 250 µA once every millisecond in order to measure
the diode temperature. Care must be taken in the PCB layout
to keep the parasitic resistance between the DIODE pin and
the MMBT3904 low so as not to degrade the measurement.
Additionally, a small 1000 pF bypass capacitor should be
placed in parallel with the MMBT3904 to reduce the effects of
noise. The temperature can be read using the READ_TEM-
PERATURE_1 PMBus command (8Dh). The default limits of
the LM5066 will cause SMBA pin to be pulled low if the mea-
sured temperature exceeds 125°C and will disable Q
temperature exceeds 150°C. These thresholds can be repro-
grammed via the PMBus interface using the OT_WARN_LIM-
IT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the
temperature measurement and protection capability of the
LM5066 are not used, the DIODE pin should be grounded.
1
, is to be measured,
1
as the layout
1
if the
17
Erroneous temperature measurements may result when the
device input voltage is below the minimum operating voltage
(10V), due to VREF dropping out below the nominal voltage
(2.97V). At higher ambient temperatures, this measurement
could read a value higher than the OT_FAULT_LIMIT, and
will trigger a fault, disabling Q
be removed and the device reset by writing a 0h, followed by
an 80h to the OPERATION (03h) register.
Damaged MOSFET Detection
The LM5066 is able to detect whether the external MOSFET,
Q
the sense resistor exceeds 4mV while the GATE voltage is
low or the internal logic indicates that the GATE should be
low,
STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD
(E1h) registers will be toggled high and the SMBA pin will be
asserted unless this feature is disabled using the
ALERT_MASK register (D8h). This method effectively deter-
mines whether Q
between the drain and gate and/or drain and source.
Enabling/Disabling and Resetting
The output can be disabled at any time during normal opera-
tion by either pulling the UVLO/EN pin to below its threshold
or the OVLO pin above its threshold, causing the GATE volt-
age to be forced low with a pulldown strength of 4.2mA.
Toggling the UVLO/EN pin will also reset the LM5066 from a
latched-off state due to an over-current or over-power limit
condition which has caused the maximum allowed number of
retries to be exceeded. While the UVLO/EN or OVLO pins can
be used to disable the output they have no effect on the
volatile memory or address location of the LM5066. User
stored values for address, device operation, and warning and
fault levels programmed via the SMBus are preserved while
the LM5066 is powered regardless of the state of the UVLO/
EN and OVLO pins.The output may also be enabled or dis-
abled by writing 80h or 0h to the OPERATION (03h) register.
To re-enable after a fault, the fault condition should be cleared
and the OPERATION (03h) register with 0h and then 80h.
The SMBus address of the LM5066 is captured based on the
states of the ADR0, ADR1, and ADR2 pins (GND, NC, VDD)
during turn on and is latched into a volatile register once VDD
has exceeded its POR threshold of 4.1V. Reassigning or
postponing the address capture is accomplished by holding
the VREF pin to ground. Pulling the VREF pin low will also
reset the logic and erase the volatile memory of the LM5066.
Once released, the VREF pin will charge up to its final value
and the address will be latched into a volatile register once
the voltage at the VREF exceeds 2.55V.
1
, is damaged under certain conditions. If the voltage across
the
EXT_MOSFET_SHORTED
1
is shorted because of damage present
1
. In this case, the faults should
bit
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