tza3005h NXP Semiconductors, tza3005h Datasheet
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tza3005h
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tza3005h Summary of contents
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... DATA SHEET TZA3005H SDH/SONET STM1/OC3 and STM4/OC12 transceiver Product specification Supersedes data of 1997 Aug 05 File under Integrated Circuits, IC19 INTEGRATED CIRCUITS 2000 Feb 17 ...
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... The TZA3005H also performs SDH/SONET frame detection. The low jitter PECL interface ensures that Bellcore, ANSI, and ITU-T bit-error rate requirements are satisfied. The TZA3005H is supplied in a compact QFP64 package. PACKAGE DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); ...
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... Fig.1 Block diagram. 3 Product specification 2 17, 18 TXSD and D TXSDQ 2 21, 20 TXSCLK and TXSCLKQ TZA3005H 62 SYNCLKDIV 63 LOCKDET 64 19MHZO 36, 37, 39, 40, 41 RXPD0 to RXPD7 47 RXPCLK CC(TXCORE) 51 GND TXCORE 38, 46 34, 42 MGS975 GND RXOUT V CC(RXOUT) GND RXCORE V CC(RXCORE) TZA3005H ...
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... LOW) I out-of-frame enable input G ground (receiver output) O frame pulse output O parallel data output 0 O parallel data output 1 S supply voltage (receiver output) O parallel data output 2 O parallel data output 3 4 Product specification TZA3005H DESCRIPTION ...
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... I parallel data input 4 I parallel data input 5 I parallel data input 6 I parallel data input 7 I transmit parallel clock input O transmit byte/nibble clock output (synchronous) O lock detect output O 19 MHz reference clock output 5 Product specification TZA3005H DESCRIPTION ...
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... V CCA(SYN) 7 AGND SYN 8 AGND SYN 9 TEST1 10 TEST2 11 GND 12 TEST3 13 REFCLKQ 14 REFCLK 15 V CC(TXOUT) 16 2000 Feb 17 TZA3005H Fig.2 Pin configuration. 6 Product specification TZA3005H 48 MRST 47 RXPCLK V CC(RXOUT RXPD7 44 RXPD6 43 RXPD5 GND RXOUT 42 41 RXPD4 40 RXPD3 RXPD2 39 V CC(RXOUT RXPD1 RXPD0 ...
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... A block diagram showing the basic operation of the chip is shown in Fig.1. The TZA3005H has a transmitter section, a receiver section, and an RF switch box. The sequence of operations is as follows: Transmitter operations: – ...
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... Using SYNCLKDIV for upstream circuits ensures a stable frequency and phase relationship is maintained between the data in to and out of the TZA3005H. For parallel-to-serial data conversion, the parallel input data is transferred from the TXPCLK byte clock timing domain to the internally generated bit clock timing domain ...
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... Out-of-frame (OOF) This is a TTL signal which enables frame pattern detection logic in the TZA3005H. The frame pattern detection logic is enabled by a rising edge on pin OOF, and remains enabled until a frame boundary is detected and OOF goes LOW. OOF is an asynchronous signal with a minimum pulse width of one RXPCLK period (see Fig ...
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... SYNCLKDIV is LOW during reset. Line loopback enable (LLEN) This is an active LOW TTL signal which selects line loopback. When LLEN is LOW, the TZA3005H routes the data and clock from the receiver inputs RXSD and RXSCLK to the transmitter outputs TXSD and TXSCLK. ...
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... RXSCLK and RXSCLKQ clock signal is present at pins RXSCLK/RXSCLKQ, there is no RXPCLK signal. This may not be suitable for some applications, in which case, the TZA3005H can be set to squelched clock operation by setting pins ALTPIN, TEST1, TEST2 and TEST3 as shown in Table 6. ...
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... OOF goes LOW, whichever occurs last. Figure 4 shows a typical OOF timing pattern when the TZA3005H is connected to a down stream section terminating device. OOF stays HIGH for one full frame after the first frame pulse (FP). The frame and byte boundary detection block is active until OOF goes LOW ...
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... OOF operating time with PM5312 STTX or PM5355 SUNI-622 (see Table 7). 2000 Feb invalid data Fig.3 Frame and byte detection. handbook, halfpage OOF FP MGK486 13 Product specification TZA3005H (28H) valid data MGK485 boundary detection enabled Fig.5 Alternate OOF timing. MGK487 ...
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... IC soldered on a standard single-sided 57 th(j-a) thick copper tracks. The measurements are performed in still air. This value will vary depending on the number of board layers, copper sheet thickness and area, and the proximity of surrounding components. 2000 Feb 17 PARAMETER PARAMETER 14 Product specification TZA3005H MIN. MAX 0.5 ...
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... note note 1 IL note mA; note note 4 terminated with 2 PECL inputs are AC coupled 15 Product specification TZA3005H and V j MIN. TYP. MAX. 3.0 3.3 5.5 0.9 1.4 2.3 272 394 420 0.8 10 + ...
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... V; minimum and maximum values are valid over entire T CC CONDITION f as Table 2; REFCLK MODE = 0 MODE = 1 in lock; note 1 frequency specification; note 1 20% to 80%; 50 load note 2 16 Product specification TZA3005H and V j MIN. TYP. MAX. 155.517 155.52 155.523 622.068 622.08 622.092 0.004 0.006 20 +20 220 450 15 ...
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... TXSCLK t h TXSD MGK490 Timing is measured from the cross-over point of the reference signal to the cross-over point of the output signal. 17 Product specification TZA3005H Fig.7 Receiver input timing Fig.9 Transmitter output timing. MGK489 MGK491 ...
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... SDPECL; PECL signal detect input 2000 Feb 17 PECL inputs handbook, halfpage 24, 27 PECL inputs handbook, halfpage PECL input handbook, halfpage 23 18 Product specification TZA3005H EQUIVALENT CIRCUIT 25, 28 100 A GND MGS979 600 600 fF ...
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... Feb 17 TTL inputs handbook, halfpage 3, 4, 10, 11 TTL inputs handbook, halfpage TTL outputs handbook, halfpage 19 Product specification TZA3005H EQUIVALENT CIRCUIT GND MGS982 100 22 GND MGS983 36 45, 47, 62 ...
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... TXSDQ; inverted serial data output 20 TXSCLKQ; inverted serial clock output 21 TXSCLK; serial clock output 2000 Feb 17 CMOS outputs handbook, halfpage PECL outputs handbook, halfpage 20 Product specification TZA3005H EQUIVALENT CIRCUIT 63 GND MGS985 V CC 17, 21 18, 20 500 A 500 A GND ...
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Acrobat reader. white to force landscape pages to be ... TZA3001 LASER 8 DRIVER TZA3005 clock CONTROLLER 8 TRANSCEIVER TZA3023 TZA3004 TZA3044 data (1) ...
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... TZA3005H using SYNCLKDIV (see Fig.14). There is no requirement specification for the propagation delay from SYNCLKDIV to TXPCLK because the TZA3005H can handle any phase relationship between these two signals. The TZA3005H internal transmitter logic must be synchronized by asserting a master reset (MRST). ...
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... Feb 17 PECL CLOCK SOURCE REFCLK TXPCLK TZA3005 ASIC parallel data 8 TXPD0 to TXPD7 Fig.13 TZA3005H in forward clocking scheme. PECL CLOCK SOURCE REFCLK TXPCLK TZA3005 ASIC parallel data 8 TXPD0 to TXPD7 SYNCLKDIV Fig.14 TZA3005H in reverse clocking scheme. ...
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... Feb 17 DATA RATE TYPE (Mbits/s) TZA3004 622 or 155 TZA3031/3001 155/622 TZA3034/3044 155/622 TZA3033/3023 155/622 PM5312 155 or 622 PM5355 622 24 Product specification TZA3005H FUNCTION clock recovery laser driver post amplifier transimpedance amplifier transport terminal transceiver Saturn user network interface ...
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... scale (1) ( 0.45 0.23 14.1 14.1 17.45 0.8 0.30 0.13 13.9 13.9 16.95 REFERENCES JEDEC EIAJ MS-022 detail 17.45 1.03 1.60 0.16 0.16 0.10 16.95 0.73 EUROPEAN PROJECTION Product specification TZA3005H SOT393 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 99-12-27 00-01-19 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 26 Product specification TZA3005H ...
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... Philips for any damages resulting from such improper use or sale. 2000 Feb 17 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 27 Product specification TZA3005H (1) REFLOW suitable suitable suitable suitable suitable ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...