l9947 STMicroelectronics, l9947 Datasheet - Page 9

• Manufacturer Part Number: l9947
• Description: Quad Half-bridge And Single High-side Driver
• Manufacturer: STMicroelectronics

Bus Timing (figure 4)
The bus signal must be defined t
CSN goes low. It is allowed to change the level of
R/WN during CSN = 0. The other signals could be
changed. To store a command it is mandatory to
fix the D0 - D3 and MODE signals t
the positive edge of CSN.
OVERCURRENT AT OUT1 - OUT5:
The output currents of OUT1 - OUT5 are inter-
nally limited. This is realized in the following way:
Figure 4: Bus and Outputs Timing Diagram
TIMING CHARACTERISTICS
t
t
(*) for t
1
7
and t
varies with the supply voltage V
Symbol
5
1
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
are derived from the internal oscillator frequency
> 100 s the latched data will be reseted due to CLEAR (status 20)
Width of CSN Low
Width of CSN High
Input Signals Before Negative Cdge of CSN
Input Signals After Positive Edge of CSN
Valid Diagnostic Data
Valid Diagnostic Data
Delay Time from Input to Power Output, VS = 13V
CSN = Low Duration (Pulse Length) for CLEAR of latched Data
Input Data Before Positive Edge of CSN Which Should be Latched
S
, relating to the output voltage slope limitation
3
9
= 1 s before
= 1 s before
Parameter
When the output current reaches a certain level
(see pag...) the Gate - Source voltage will be
clamped to a lower level. The output current is
now limited and follows the output ID, UDS char-
acteristic for this Gate - Source voltage. An inter-
nal timer starts when the output voltage drop
(Drain - Source) increases above 0.4V
After 100 s typ. the output is switched OFF and
the corresponding overcurrent bit (OVC1 or
OVC2) will be set. The outputs can be activated
again with the next input data word.
Min.
100
20
10
1
1
1
Typ.
Max.
300
90*
10
10
S
.
L9947
Unit
s
s
s
s
s
s
s
s
s
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