W134 Cypress Semiconductor Corp., W134 Datasheet

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... STOPB Cypress Semiconductor Corporation Document #: 38-07426 Rev. ** Direct Rambus™ Clock Generator Overview The Cypress W134M/W134S provides the differential clock signals for a Direct Rambus memory subsystem. It includes ® signals to synchronize the Direct Rambus Channel clock to an Chan- external system clock but can also be used in systems that do not require synchronization of the Rambus clock ...

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... Clock Output Enable: When this input is driven to active LOW, it disables the differential Rambus Channel clocks. I Active LOW Power-Down: When this input is driven to active LOW, it disables the differential Rambus Channel clocks and places the W134M/W134S in power-down mode. I PLL Multiplier Select: These inputs select the PLL prescaler and feedback divid- ers to determine the multiply ratio for the PLL for the input REFCLK ...

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... Phase Detector. When the clocks are aligned, data can be exchanged directly from the Pclk domain to the Synclk domain. Table 1 shows the combinations of Pclk and Busclk frequen- cies of greatest interest, organized by Gear Ratio. Figure 2. Gear Ratio Timing Diagram W134M/W134S Busclk equal. In one ...

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... DC voltage V V X,STOP W134M/W134S 1.33 267 MHz 300 MHz 400 MHz 400 MHz Busclk RAC DLL W134M Mult1 given in Table 14. The level of X,STOP is set by an external resistor network. 1.0 W134S Page ...

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... Power-down mode. Synclk 100 100 6 V Turn- Normal Power-Down C Figure 4. Clock Source State Diagram W134M/W134S PwrDnB Clk 1 PAclk 0 GND (in MHz) at the Phase Detector, and V , may remain on or may DDR DDPD Ratio 1 1.33 ...

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... Figure 5. State Transition Timing Diagrams t t POWERUP CLKSETL Clock output settled within Clock enabled the phase before and glitch free disabled Figure 6. Multiply Transition Timing t MULT W134M/W134S Clock PwrDnB StopB Source 0 X OFF POWERDN STOP t ...

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... Table 14. The outputs are in a high-imped- CLKON CLKSETL ance state during the Clk Stop mode. W134M/W134S Description Time from PwrDnB to Clk/ClkB output settled (excluding t ). DISTLOCK Time from PwrDnB until the internal PLL and clock has turned ON and settled ...

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... Leave pads for future use. F Document #: 38-07426 Rev. ** Units ms Time from when Clk/ClkB output is settled to when the phase error between SynclkN and PclkM falls within the t Description Description with respect to ground DD Description W134M/W134S Description spec in Table 14. ERR,PD Min. Max. -- 250 -- 65 -- 100 ...

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... The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%. Document #: 38-07426 Rev. ** Description [2] [4] [4] < 100 mV. AC W134M/W134S Min. Max. Unit 3.135 3.465 ° ...

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... This is defined at the output pins. OUT O O Ordering Information Package Ordering Code Name W134M/W134S H Document #: 38-07426 Rev. ** Description [6] [6] [7] [7] [8] [9] Package Type 24-pin SSOP (150 mils) W134M/W134S Min. Max. Unit 2.5 3. 100 ps - 100 ps - 160 –100 100 ps –100 ...

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... FB = Dale ILB1206 - 300 (300 @ 100 MHz VIA to GND plane layer All Bypass cap = 0.1 Ceramic XR7 Document #: 38-07426 Rev. ** +3.3V Supply 0.005 W134M/W134S Page ...

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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W134M/W134S Page ...

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... Document Title: W134M/W134S Direct Rambus™ Clock Generator Document Number: 38-07426 Issue REV. ECN NO. Date ** 115531 05/10/02 Document #: 38-07426 Rev. ** Orig. of Change DSG Change from Spec number: 38-00822 to 38-07246 W134M/W134S Description of Change Page ...