l6611 STMicroelectronics, l6611 Datasheet - Page 4

• Manufacturer Part Number: l6611
• Description: Digitally Programmable Secondary Housekeeping Controller
• Manufacturer: STMicroelectronics

PIN DESCRIPTION (continued)
L6611
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Pin #
10
11
12
13
14
15
16
17
4
5
6
7
8
9
DFAULT
PS-ON /
PW-OK
ACsns
PROG
Dmon
Name
Clock
VREF
/Data
Aout
Cout
-12V
GND
Ainv
Cinv
Vdd
Output of the error amplifier for the main converter. This pin typically drives an optocoupler and is
also used for compensation along with Ainv (pin #5).
Main loop error amplifier inverting input. The non-inverting input is connected to an internal 2.5V
reference that can be digitally trimmed. A high impedance internal divider from +12V and +5V
UV/OV sense pins (#19, #20) eliminates the need for external divider in most applications. The
pin is used for error amplifier compensation.
Auxiliary loop optocoupler drive. Also node for error amp compensation. Large signal slew rate is
limited to reduce sensitivity to switching noise.
Inverting input for Auxiliary error amplifier. The non-inverting input is connected to an internal
1.25V reference that can be digitally trimmed.
Dual or Auxiliary UV/OV monitor, Dmon is programmable to monitor 3V3 or 5V. To allow a correct
power up, the UV function on this pin is blanked out during initial start-up. There is no delay for
the OV function.
Dual or Auxiliary fault protection. When Dmon (#8) recognizes an over voltage, DFAULT and
MFAULT (#1) go high. DFAULT is capable of sourcing up to 50mA. Possible applications are a
crowbar across the Auxiliary output or an opto-coupled fault signal to the primary side.
Positive input supply voltage. Vdd is normally supplied from the Auxiliary power supply output
voltage. If Vdd-UVL detects a sustained under voltage, PW-OK (#12) will be pulled low and
sending MFAULT (#1) high will disable the main converter.
Analog of bulk voltage for AC fail warning. The usual source of this analog pin is one of the
secondary windings of the main transformer. Hysteresis is provided through a trimmable 50 A
current sink on this pin that is activated as the voltage at the pin falls below the internal reference
(2.5V).
Power good signal for the Main converter. When asserted high, this pin indicates that the
voltages monitored are above their UV limits. There will be typically 250ms delay from the Main
outputs becoming good and PW-OK being asserted. This is nominally an open drain signal. To
improve robustness, this output has a limited current sink capability. In programming mode, this
pin is used for data input; then the absolute maximum rating will be Vdd+0.5V.
Control pin to enable the Main converter. This pin has debouncing logic. A recognized high value
on this pin will cause PW-OK (#12) to go immediately low and, after a delay of 2.5ms, to shut
down the main PWM by allowing MFAULT (#1) to go high. During normal operation (or if not
used) this pin has to be connected to a voltage lower than 0.8V. In programming mode, this pin
will be used to clock serial data into the chip.
2.5V reference for external applications. This is a buffered pin. Shorting this pin to ground or to
Vdd (#10) will not affect integrity of control or monitor references. An external capacitor (max.
100nF) is required whenever the pin is loaded (up to 5 mA), otherwise it can be left floating.
-12V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VREF, #14), the function
will be disabled.
Ground pin. The connection integrity of this pin is constantly monitored and in case of either a
bond wire or a PCB trace going open, MFAULT (#1) and DFAULT (#9) will be forced high
switching off the supply.
The chip has 2 operating modes, depending on PROG input pin biasing:
– normal mod e: PROG should be floating or shorted to ground;
– programming mod e: forcing PROG high (+5V), the chip enters programming mode. PW_OK
(#12) and PS_ON (#13) pins are disconnected from their normal functionality and they become
inputs for DATA and CLOCK allowing the chip to be programmed. The programming mode al-
lows selecting some options and adjusting some setpoints;
Description