lx64eb Lattice Semiconductor Corp., lx64eb Datasheet - Page 5
lx64eb
Manufacturer Part Number
lx64eb
Description
High Performance Interfacing And Switching
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.LX64EB.pdf
(72 pages)
- Current page: 5 of 72
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Lattice Semiconductor
Figure 2. GDX Block
The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-
ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-
ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
combined as one shift register via the GRP.
GRP
32 bits
4 bits
4 bits
4 bits
4 bits
16 bits
16 bits
16 bits
4
4
4
Control
8
Select
8
8
8
MUX
8
2
2
2
8
8
8
8
2
2
2
2
GDX Block
Control Array
5
MRBs 12-15
MUX and Register
MUX and Register
MUX and Register
MUX and Register
MRBs 8-11
MRBs 4-7
Nibble 0
Nibble 1
Nibble 2
Nibble 3
Block (MRB)
Block (MRB)
Block (MRB)
Block (MRB)
0
1
2
3
ispGDX2 Family Data Sheet
sysIO Bank
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
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