atmega3250v-8auatmega325v-8ai ATMEL Corporation, atmega3250v-8auatmega325v-8ai Datasheet - Page 182
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atmega3250v-8auatmega325v-8ai
Manufacturer Part Number
atmega3250v-8auatmega325v-8ai
Description
Atmega3250 8-bit Microcontroller With In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA3250V-8AUATMEGA325V-8AI.pdf
(362 pages)
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ATmega325/3250/645/6450
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 20-10. USBS Bit Settings
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 20-11. UCSZ Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 20-12. UCPOL Bit Settings
UCPOLn
UCSZn2
0
0
0
0
1
1
1
1
0
1
USBSn
0
1
Transmitted Data Changed
(Output of TxD Pin)
Rising XCK Edge
Falling XCK Edge
UCSZn1
0
0
1
1
0
0
1
1
UCSZn0
0
1
0
1
0
1
0
1
Received Data Sampled
(Input on RxD Pin)
Falling XCK Edge
Rising XCK Edge
Stop Bit(s)
1-bit
2-bit
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
2570L–AVR–08/07
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