atmega3250v-8auatmega325v-8ai ATMEL Corporation, atmega3250v-8auatmega325v-8ai Datasheet - Page 89

• Manufacturer Part Number: atmega3250v-8auatmega325v-8ai
• Description: Atmega3250 8-bit Microcontroller With In-system Programmable Flash
• Manufacturer: ATMEL Corporation

15.6.1
15.7
2570L–AVR–08/07
Modes of Operation
Compare Output Mode and Waveform Generation
Figure 15-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform
Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis-
ible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on
the OC0A Register is to be performed on the next compare match. For compare output actions
in the non-PWM modes refer to
on page
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0A strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output
mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM
output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM
modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a
compare match
For detailed timing information refer to
in
“Timer/Counter Timing Diagrams” on page
96, and for phase correct PWM refer to
See “Register Description” on page 95.
COMnx1
COMnx0
FOCn
clk
(See “Compare Match Output Unit” on page
I/O
Waveform
Generator
Table 15-3 on page
Figure
D
D
D
PORT
ATmega325/3250/645/6450
DDR
OCnx
94.
15-8,
Q
Q
Q
Table 15-5 on page
Figure
96. For fast PWM mode, refer to
15-9,
88.).
1
0
Figure 15-10
97.
OCn
Pin
and
Figure 15-11
Table 15-4
89