mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 263
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mc9s08dz32amlfr
Manufacturer Part Number
mc9s08dz32amlfr
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08DZ32AMLFR.pdf
(458 pages)
- Current page: 263 of 458
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The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
12.3.4.1
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Freescale Semiconductor
Reset:
W
R
1
MSCAN Receiver Flag Register (CANRFLG)
WUPIF
This setting is not valid. Please refer to
TSEG13
Bit Time
1
0
7
This setting is not valid. Please refer to
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
Figure 12-8. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
CSCIF
=
6
0
TSEG12
(
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
f CANCLK
MC9S08DZ128 Series Data Sheet, Rev. 1
TSEG21
Table 12-7. Time Segment 2 Values
Table 12-8. Time Segment 1 Values
RSTAT1
0
0
1
1
:
0
5
TSEG11
0
0
1
1
1
1
:
Table 12-7
Table 12-35
TSEG20
RSTAT0
)
•
Table 12-35
4
0
0
1
0
1
:
(
1
TSEG10
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
+
and
TimeSegment1
0
1
0
1
0
1
:
for valid settings.
TSTAT1
Table
for valid settings.
0
3
Time Segment 2
1 Tq clock cycle
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
12-8).
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
1 Tq clock cycle
4 Tq clock cycles
TSTAT0
:
2
0
+
TimeSegment2
:
1
1
OVRIF
1
1
0
1
)
Eqn. 12-1
RXF
0
0
263
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