mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 442
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mc9s08dz32amlfr
Manufacturer Part Number
mc9s08dz32amlfr
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08DZ32AMLFR.pdf
(458 pages)
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Appendix A Electrical Characteristics
A.12.4
Table A-16
442
1
2
3
4
5
and
SPI
Num
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
Refer to
All timing is shown with respect to 20% V
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
10
11
12
1
2
3
4
5
6
7
8
9
Figure A-15
1
Figure A-15
C
D
D
D
D
D
D
D
D
D
D
D
D
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time
Master and Slave
Clock (SPSCK) low time Master
and Slave
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
Operating Frequency
through
through
Table A-16. SPI Electrical Characteristic
MC9S08DZ128 Series Data Sheet, Rev. 1
Rating
Figure A-18
Figure
3
4
2
5
A-18.
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
DD
describe the timing requirements for the SPI system.
and 70% V
Symbol
t
t
t
t
t
t
t
t
SCKH
SCKL
t
t
SI(M)
HI(M)
t
t
SI(S)
HI(S)
Lead
Lead
t
t
t
t
t
SCK
SCK
Lag
Lag
f
f
SO
SO
HO
HO
t
dis
op
op
A
DD
, unless noted; 100 pF load on all SPI
1/2 t
1/2 t
f
Bus
SCK
SCK
Min
–10
–10
2.5
1/2
1/2
DC
30
30
30
30
25
25
—
—
—
/2048
2
0
– 25
– 25
f
f
2048
Max
Bus
Bus
1/2
1/2
—
—
—
—
—
—
—
—
—
40
40
—
—
—
—
/2
/4
Freescale Semiconductor
t
t
t
t
Unit
SCK
SCK
SCK
SCK
t
t
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
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