mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 115

• Manufacturer Part Number: mc9s12uf32
• Description: System Chip Guide V01.05
• Manufacturer: Freescale Semiconductor, Inc

A.4 Reset, Oscillator and PHY
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
USB Physical Layer (PHY).
A.4.1 Startup
Table A-12 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG_U) Block User Guide.
A.4.1.1 POR
The release level V
if the device is powered externally. After releasing the POR reset, the oscillator is started.
A.4.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
the PORF bit in the CRG_U Flags Register has not been set.
A.4.1.3 External Reset
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector if there was an oscillation before reset.
A.4.1.4 Stop Recovery
Out of STOP, the controller can be woken up by an external interrupt.
Freescale Semiconductor
Conditions are shown in Table A-4 unless otherwise noted
Num
1
2
3
4
5
6
C
D
D
D
D
T
T
DD
POR release level
POR assert level
Reset input pulse width, minimum input time
Startup from Reset
Interrupt pulse width, IRQ edge-sensitive
mode
Wait recovery startup time
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
PORR
and the assert level V
Table A-12 Startup Characteristics
Rating
PORA
are derived from the V
System on a Chip Guide — 9S12UF32DGV1/D V01.05
RSTL
Symbol
PW
PW
V
V
n
t
PORR
PORA
WRS
RST
RSTL
IRQ
, the CRG_U module generates an internal
0.97
Min
192
20
2
DD
Supply. They are also valid
Typ
Max
2.07
196
14
Unit
n
t
t
ns
osc
cyc
V
V
osc
115